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Maybe this opamp architecture might help you meet the specs (this design simulated DC gain of 80 dB, GBW of 1.4 GHz and phase margin of 62 deg in TSMC 0.35 um CMOS technology) , though you may have have some difficulty with Vdd = 1.8 V :
I've used the topology described in these papers and it works very well. The amplifier I designed had specifications very similar to the ones the thread starter is wanting to meet. I think I had a larger supply voltage though.
The ft of the mos transistor is expressed approximately to the equation " ft=u*(vgs-vt)/2/pi/L^2". Therefore, short-length mos transistors have higher ft than long-length ones.
I designed such an opamp use 0.25u and the power supply is 2.5V, the opamp is a fully diffrential gain-boosted telescopic opamp.
As 1.8v process and i think two stage maybe a choince but i am not sure.
shaq said:
ericliu said:
Please refer to the paper "A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at nyquist input, jssc,vol. 36 no. 12 Dec. 2001". A two-stage amplifer has been presented with 100-dB of open loop gain and 2-GHZ GBW by using the 0.35-um CMOS process.
You could also use a fully differential opamp with gain boosting to get 1GHz.
Check out:
A compensation-based optimization methodology for gain-boosted opamp
Jie Yuan; Farhat, N.;
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Volume 1, 23-26 May 2004 Page(s):I - 669-72 Vol.1
Digital Object Identifier 10.1109/ISCAS.2004.1328283
Abstract | Full Text: PDF(262 KB) IEEE CNF
Rights and Permissions
A gain-boosted OPAMP design methodology is presented.
The methodology provides a systematic way of gain-boosted
OPAMP optimization in terms of AC response and settling
performance. The evolution of the major poles and zeros of
the gain-boosted OPAMP is studied, which reveals the rationale
behind our optimization effort. A sample OPAMP
was implemented in 0.6 μm CMOS technology. It achieves
a DC gain of 88dB, a bandwidth of 725MHz with 49◦ phase
margin and a 0.1% settling time of 4.5ns. The sample/hold
front-end of a 12-bit 50MSample/s ADC was implemented
with this OPAMP. It achieves an SNR of 78dB for an 8.1MHz
input signal.
You could also use a fully differential opamp with gain boosting to get 1GHz.
Check out:
A compensation-based optimization methodology for gain-boosted opamp
Jie Yuan; Farhat, N.;
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Volume 1, 23-26 May 2004 Page(s):I - 669-72 Vol.1
Digital Object Identifier 10.1109/ISCAS.2004.1328283
Abstract | Full Text: PDF(262 KB) IEEE CNF
Rights and Permissions
A gain-boosted OPAMP design methodology is presented.
The methodology provides a systematic way of gain-boosted
OPAMP optimization in terms of AC response and settling
performance. The evolution of the major poles and zeros of
the gain-boosted OPAMP is studied, which reveals the rationale
behind our optimization effort. A sample OPAMP
was implemented in 0.6 μm CMOS technology. It achieves
a DC gain of 88dB, a bandwidth of 725MHz with 49◦ phase
margin and a 0.1% settling time of 4.5ns. The sample/hold
front-end of a 12-bit 50MSample/s ADC was implemented
with this OPAMP. It achieves an SNR of 78dB for an 8.1MHz
input signal.
You could also use a fully differential opamp with gain boosting to get 1GHz.
Check out:
A compensation-based optimization methodology for gain-boosted opamp
Jie Yuan; Farhat, N.;
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Volume 1, 23-26 May 2004 Page(s):I - 669-72 Vol.1
Digital Object Identifier 10.1109/ISCAS.2004.1328283
Abstract | Full Text: PDF(262 KB) IEEE CNF
Rights and Permissions
A gain-boosted OPAMP design methodology is presented.
The methodology provides a systematic way of gain-boosted
OPAMP optimization in terms of AC response and settling
performance. The evolution of the major poles and zeros of
the gain-boosted OPAMP is studied, which reveals the rationale
behind our optimization effort. A sample OPAMP
was implemented in 0.6 μm CMOS technology. It achieves
a DC gain of 88dB, a bandwidth of 725MHz with 49◦ phase
margin and a 0.1% settling time of 4.5ns. The sample/hold
front-end of a 12-bit 50MSample/s ADC was implemented
with this OPAMP. It achieves an SNR of 78dB for an 8.1MHz
input signal.
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