Delta Sigma ADC - Latched Comparator Testing

[sammyt09]

latched comparator

Hi,

I wonder if somebody could please be of help?

I have implemented a latched comparator, which is part of a delta sigma ADC. I am currently testing it to validate it's performance. I am running the Cadence ADE environment. So far, I have only done transient analyses to check H->L and L->H transitions.

I have two questions:

1) What is the best method to measure the input offset of a latched comparator? Which inputs (clk, vin_n and vin_p) should be swept and which should be held? How is the input offset defined?

2) What is the best method to measure hysteresis of a latched comparator? Again, how is this value defined?

Any help or references would be very useful. Thanks kindly in advance!



sammyt09

 

[erikl]

delta sigma adc schematic

...
I have implemented a latched comparator, ...
sammyt09

Do you talk about schematic or extracted layout?
From a totally symmetric schematic design you won't be able to find an offset unless you run Monte Carlo simulations (and if the fab-process-related MC setUp is available in your PDK). Simulation on extracted layout might produce offset due to layout asymmetries, but not only from those of the input transistors.

The same is valid for hysteresis (as long as you don't include positive feedback, of course).

 

[sammyt09]

delta sigma adc

Hi erikl,

Thanks for your response.

I have implemented this latched comparator purely in a schematic form at the moment.

Ultimately, what I am looking for is a testbench in which I could gather all the important information about the comparator (preferably in one go). I would like to perform tests across corners as well, so if there is a recognised testbench setup in which I could do this, I would be very grateful if you (or anyone else) could help me with.


Regards

sammyt09

 

[fredcadete]

I am probably too late, but here goes. I hope it helps someone else.

Make a transient analysis with a very slow input signal, switching up and down more than your expected offset. Meaning, if you expect an offset of 5mV, make the differential input go from -10mV to 10mV, and back down.

Then you have to measure your differential input when the output switches from low to high and form high to low, like if you use spice measures:

.measure TRAN triprise FIND v(vid) WHEN v(o)='vdd/2' RISE=LAST
.measure TRAN tripfall FIND v(vid) WHEN v(o)='vdd/2' FALL=LAST

Then you have 'triprise' and 'tripfall' as your two trip points. Their average is your offset, and their difference is your hysteresis width.

This only works for latched, asynchronous comparators obviously.