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Delays/Jitters problem in data lines with same clock

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maqbool_sid

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Hi ,

I have a PCB with 8 differential pairs. All are matched length.

All pairs are connected to a FPGA through bus isolators and on the other end of each trace, an SMA has been placed to check the results. No terminations has been used.

When I apply same clock to all pairs, ranging from 1Mhz to 150Mhz, I got waveforms of different timing at the other end of differential pairs.

Attached are some pictures for more clarification.

Looking forward for the response.

Regards,
Maqbool

These are the pictures attached:
 

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