Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Delays/Jitters problem in data lines with same clock

Status
Not open for further replies.

PCB Designers

Member level 3
Member level 3
Joined
Dec 17, 2009
Messages
65
Helped
6
Reputation
12
Reaction score
8
Trophy points
1,288
Location
Karachi, Pakistan
Visit site
Activity points
1,700
Hi ,

I have a PCB with 8 differential pairs. All are matched length.

All pairs are connected to a FPGA through bus isolators and on the other end of each trace, an SMA has been placed to check the results. No terminations has been used.

When I apply same clock to all pairs, ranging from 1Mhz to 150Mhz, I got waveforms of different timing at the other end of differential pairs.

Attached are some pictures for more clarification.

Looking forward for the response.

Regards,
Maqbool

These are the pictures attached:
 

Attachments

  • 1_1.JPG
    1_1.JPG
    160.3 KB · Views: 120
  • 2_2.JPG
    2_2.JPG
    127.9 KB · Views: 109
  • 3_3.JPG
    3_3.JPG
    127.1 KB · Views: 104
  • 4_4.JPG
    4_4.JPG
    125.4 KB · Views: 101
  • 5_5.JPG
    5_5.JPG
    124.5 KB · Views: 97
  • 6_6.JPG
    6_6.JPG
    124.1 KB · Views: 105
  • 7_7.JPG
    7_7.JPG
    169.6 KB · Views: 110
Last edited:

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top