Hi
In your program, you tried to synchronize some process with clock. But you have done it inside the process. It doesn't work.
If you want synchronize the design with a clock, you should check the clock trigger at the beginning of the program.
And also the loop statement doesn't work, because it cannot be implemented in hardware.
You can change the program like this:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY soft_switching IS
PORT
(
pwm : IN STD_LOGIC;
ilt : IN STD_LOGIC;
clk : IN STD_LOGIC;
pwm_delay : OUT STD_LOGIC;
tab : OUT STD_LOGIC;
tl : OUT STD_LOGIC
);
END soft_switching;
-- Architecture Body
ARCHITECTURE soft_switching_architecture OF soft_switching IS
SIGNAL flag : bit;
SIGNAL pwm_temp : STD_LOGIC;
signal counter : std_logic_vector(4 downto 0) ;
BEGIN
p01: process(clk,pwm) is
begin
if (clk'event AND clk = '1' AND clk'last_value = '0') then
if (counter="10100") then
if pwm='1' then
pwm_delay <= '1';
else
pwm_delay <= '0';
end if;
counter <="00000";
else
counter <= counter + 1;
end if;
end if;
end process p01;
END soft_switching_architecture;
In fact, I could not catch what you are planning to do. But this is the right modification for the program given by you.
For the counter variable, you can change the length of the vector based on your requirement.
Regards,
Vishwa