Delay in Signal update

[hithesh123]

I am writing a testbench to read a register. For some reason the RD, CS signals are getting update a couple of nanoseconds after the clock. This delay increases as clock cycles increase.
At the first rising edge of the clock, ther is no delay. At the second edge, there is 1ns delay, at 4th there is 2ns etc.
(see simulation waveforms)

----MCU clock----
             PROCESS
	     BEGIN
  	     Clk_Mcu<='0';
  	     WAIT FOR 10.416 NS;
  	     Clk_Mcu<='1';
  	     WAIT FOR 10.416 NS;
	     END PROCESS;
	     
	     
  ----- READ/WRITE TO A REGISTER --------
  ----- 20.833 NS = 48 MHz ------
    PROCESS
      VARIABLE temp, addr, read_data, write_data : STD_LOGIC_VECTOR(15 DOWNTO 0):= X"0000";      
      BEGIN
        ---- READ ----
        write_data:=b"0000000000000100";  
        rd_n<='1';      -- INITIAL VALUES
        cs_n<='1';      -- INITIAL VALUES
        ale<='0';       -- INITIAL VALUES
        WAIT FOR 10.416 NS;   -- FIRST HALF BCLK. DON'T DO ANYTHING.
        addr:=X"0100";      -- COUNTER GLOBAL CONTROL REG
        AD<=addr;
        cs_n<='0';      -- MAKE CHIP SEL LOW  
        ale<='1';       -- MAKE ALE HIGH FOR ONE BCLK CYCLE
        WAIT FOR 20.833 NS;
        ale<='0';
        WAIT FOR 10.416 NS;
        AD<=(OTHERS=>'Z');  -- TRISTATE THE AD BUS
        WAIT FOR 10.416 NS;
        rd_n<='0';      -- MAKE READ LOW FOR 2 CLK CYCLES
        WAIT FOR 20.833 NS;
        read_data:=AD;      -- WAIT FOR 1 BCLK AND READ THE DATA ON THE AD BUS
        WAIT FOR 20.833 NS;
        rd_n<='1';
        cs_n<='1';      -- DE-SELECT CHIP
        WAIT FOR 20.833 NS; 
        WAIT FOR 20.833 NS;      
      END PROCESS;

 

[TrickyDicky]

first of all, I see this:

WAIT FOR 10.416 NS;

have you set molelsim's timing resolution to 1ps? the default is 100 ps. otherwise it will just run at 100MHz

You have very precise timings in your testbench. can you not just make then related to clock, instead of absolute timings?
eg: eait until rising_edge(clk)

or 10 clocks:

for i in 1 to 10 loop
  wait until rising_edge(clk);
end loop;

..etc

the signals being out by a couple of nanoseconds it probably down to the resolution of your simulator.

 

[hithesh123]

I don't need such precise timing. Initially, it was just 20.8ns and 10.4 ns.
I thought the 1ns delay was because of the non-precise timing.

I just changed the resolution to 1ps. Now the clk edges are aligned with the signals.
Isn't 100ps enough. I don't understand what you meant by " otherwise it will just run at 100MHz"

 

[TrickyDicky]

100ps would be enough for specs of 20.8, 10.4 etc. But in your origional code, you have 1ps resolution specified with your waits.

I didnt mean exactly 100MHz, the simulator can only run at whatever the minimum resolution is.

 

[hithesh123]

Ok, thanks.
Unrelated vhdl question - what is the equivalent of

port_a equ 0x100; in vhdl?