Verilog code maps to the luts, registers and rams inside the FPGA device during compilation. So it can be classed as a hardware implementation.
I dont quite know what you mean?
A small change to the code may only mean a minor functional change, but the internal of the FPGA will probably be placed completly differently. But as long as you have decent timing specs you wouldnt notice any difference externally.
I mean, the small change may lead to different energy or performance metric values, such as throughput, energy, power, etc, so this feature may limit the comparisons between physical metrics.
throughput is a question of function, not placement.
Energy is more a case of logic usage and data throughput.
Are you proposing designing an FPGA with an asynchronous design inside?
I think a security circuit must be an asynchronous design. I think these physical metrics much relate to the structure of the circuit, which is synthesized from a behavior verilog code. This means different structures from different codes will get different metric values.
Since when do they have to be asynchronous? I've been working around systems that encrypt data and pretty much all of the designs used some sort of pipelined encryption engine. Otherwise you can't get enough performance out of them and/or you need too many copies of the encryption engine.
Regards
So does this relate to the original question/
I have thought that the function change may lead to longer critical path thus affect throughput, max frequency, or more logic unit as well as different switching factor.What metrics?
It all depends what the function change is.
Basically: more logic used = more power. Thats about the only thing I can think that may change much (if at all). FPGAs are quite power hungry devices.
If you have a fully synchronous design, with good timing specs, then if it meets the specs, it should work.
Let me put it in another way. Does a completely different internal FPGA connection due to a minor functional change lead to quite different metrics measure values?
assign g = a ? c : b;
assign g = a ^ (c & b | d);
assign g = b ? (a ? f : e) : (a ? d : c);
assign g[15:0] = a ? c[7:0] : b[7:0];
assign g[15:0] = a ? c[7:0] * b[7:0] : c[7:0] + b[7:0];
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