Defining a constant using for loop (VHDL)

Status
Not open for further replies.

darshkamal

Junior Member level 1
Joined
Nov 7, 2011
Messages
18
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,443
Hello
Usually when I want to something to syntesized as a memory, I declare it as a constant. For example as
Code:
type my_array3 is array (0 to 4) of sfixed(7 downto -8) ;
constant main_angles: my_array3 :=(to_sfixed(0.0,7,-8),to_sfixed(1.5708,7,-8),to_sfixed(3.1416,7,-8),to_sfixed(4.7124,7,-8),to_sfixed(6.2832,7,-8));
and these 2 lines are located in a package

Now I want to define a constant that will hold 1024 values and I want to use a for loop to facilate the matters and not write 1024 value by hand.
As an example
Code:
for i IN 0 to 1023
constant A(i):=i;

I don't know the right syntax or if the for loop can be used inside a process only or not.
Can anyone help please ?
 

Sounds like a job for a generate statement or a function.
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…