[SOLVED] `define under the `ifdef and `elsif in verilog

[imbichie]

Hi all,

Is it possible to define the `define under the `ifdef and `elsif in verilog for synthesis.

When I did the same, it is simulating well, but when I synthesized the code its saying that the deines under teh `ifdef or `elsif are undeclared.

example:

`define X
`define Y
`define Z

`ifdef X
  `define a 2
  `define b 3
`elsif Y
  `define a 1
  `define b 1
`elsif Z
  `define a 2
  `define b 1
`endif

here the defined parameters a and b are showing as undeclared during synthesis...

Thanks in Advance

 

[FvM]

I guess, the problem hasn't to do with `ifdef usage. You are probably missing the required syntax for text macro insertion.

a will be undeclared, you'll write `a.

 

[imbichie]

Hi FvM,
Thank you for your reply.
I was using the `a.
The define parameters are defined in params.v file.
But the thing is that during the simulation I commented the `include "./params.v" file in that module, and I added the ./params.v in the filelist. (otherwise it was giving error like the `include "./params.v" file is unable to open).
But when I was synthesizing the same code, I forgot to un-comment the `include "./params.v", so that is why the error came.
Once I un-commented the same the error gone and its working fine.