Mar 23, 2018 #1 S sai_shashi Junior Member level 3 Joined Jan 20, 2017 Messages 25 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 240 Hi All, I know that the default values of wire and reg in verilog are z and x respectively. can someone tell me why it is so? Thanks shashi
Hi All, I know that the default values of wire and reg in verilog are z and x respectively. can someone tell me why it is so? Thanks shashi
Mar 23, 2018 #2 T ThisIsNotSam Advanced Member level 5 Joined Apr 6, 2016 Messages 2,549 Helped 397 Reputation 794 Reaction score 464 Trophy points 1,363 Activity points 14,768 Wires typically are used for 'connectivity'. Unconnected? z. Regs typically are used for 'storage'. No value stored? x.
Wires typically are used for 'connectivity'. Unconnected? z. Regs typically are used for 'storage'. No value stored? x.