But I'm not equipped with any problem where this behaviour would matter.
I'm not aware of additional comments in the IEEE specification relevant for this discussion, but I didn't miss them so far.
Im sure that the default statement must be ignored for a full case statement (respectively an empty default set).
You can not change the synthesized result by adding a "default" to a "full" case, since the synthesized hardware can only see '0' and '1'. You should make the simulation as safe as possible by adding a "default" that propagates 'X' to the output signals.How do you know this that the default statement must be ignored for a full case statement ?
You can not change the synthesized result by adding a "default" to a "full" case, since the synthesized hardware can only see '0' and '1'.
The synthesis tool will only consider case options with '0' and '1', so if all combinations for '0' and '1' are specified, the default will be ignored (for synthesis).What do you want to say by the above quote. It was not much clear. Can you please clarify and provide additional things related to the quote.
STD_MATCH
Thanks for clarify many issues and double reply. Though many things are clear , one questions is not still clear. That question is : What do u want to mean by "The synthesis tool will only consider case options with '0' and '1', so if all combinations for '0' and '1' are specified, the default will be ignored (for synthesis)"?
I repeat another question which is not still answered clearly:
How do you know/conclude that the default statement must be ignored for a full case statement ? Have u conducted any experiment or have you see any valid authenticated document?
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