deep subthreshold region operation of MOSFET

[transign]

Can we assume that if vgs<vth a transistor operates in the deep triode region? Is there something we should take care of when we design in this region?
In virtuoso deep triode region is region 3? I would like to learn more about the design of the deep triode region so if you have any recommendations feel free to share

 

[Mahmoud_Sofy]

In subthreshold you can use the exponential model of the bjt where its base is coupled to the gate of the mosfet with capacitive divider, but operating in such region is not too beneficial and let me explain it more:
When you are going in weak inversion (wi) direction (subthreshold) you are losing speed to get higher gain, and vice versa, we go to stronger inversion (si) to have higher speed and lower gain
What is really happening at extremes is that your gain will saturate as you go deeper into subthreshold, and speed also will saturate as you go deeper into strong inversion
So the "sweet spot" is the moderate inversion region (region between si and wi) which gives you the best trade off, but in this region there is no valid simple models as there was for wi and si (exponential and square law models respectively) so we need to find out some way to make use of the complex models spices use, and gm/id methodology (aka V*) is that systematic approach which you can use to design in any inversion level really with the best accuracy
For more details you can check "systematic design of analog cmos circuits" book by jespers and murmann