Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

DEEP nWELL for negative voltages

Status
Not open for further replies.

YESH_23

Member level 4
Joined
Dec 20, 2005
Messages
78
Helped
8
Reputation
16
Reaction score
4
Trophy points
1,288
Location
INDIA
Activity points
1,951
deep nwell

can any one help me in learning deep n well.

why is it used.?

how is it fabricatrd.?

the way it is connected in the layout......

THANX in advance
 

joely2k

Member level 1
Joined
Dec 4, 2005
Messages
36
Helped
4
Reputation
8
Reaction score
3
Trophy points
1,288
Activity points
1,595
deep n well

what u meaning? DEEP & WELL or "DEEP nWELL"
??
 

Syukri

Full Member level 5
Joined
Aug 9, 2005
Messages
252
Helped
24
Reputation
48
Reaction score
10
Trophy points
1,298
Location
Malaysia
Activity points
3,960
deep n-well

Drawn in layout is still the same..but the diffusionmust be strong to penetrate deep to the p substarte

Added after 39 seconds:

n well in layout is reresent by the the less dopant of n type
 

vbhupendra

Full Member level 4
Joined
May 11, 2005
Messages
235
Helped
15
Reputation
30
Reaction score
8
Trophy points
1,298
Location
GOA, INDIA
Activity points
3,219
deep n well process

Deep nwell are basically used for isolation.Deep N-well or buried N-well is a nwell layer implanted deeper down in the substrate than the normal N-well. It is mainly to control the substrate leakage of N-mos and to provide the better isolation.These processes mainly used for high frequency (RF) circuits.
 

wan

Junior Member level 2
Joined
Aug 24, 2005
Messages
23
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,505
deep nwell process

YESH_23 said:
weather we can put psub2 on deep n well


No, psub2 is used only for distinguishing differential gnd connectted to sub.
Deep nwell is formed by long time annealing and drivering fellowed implantion and a buried N+ layer is formed. With fellowing Nwell step, a p-type island will be surrounded by N+ area lateral and lognitudinal, So noise can be isolated. Deep Nwell is often used in RFIC,especially in PA.
 

qslazio

Full Member level 3
Joined
May 23, 2004
Messages
176
Helped
18
Reputation
36
Reaction score
7
Trophy points
1,298
Activity points
1,420
deep n well structure

Deep N well is used to isolate to substrate noise.
The area will be about 1.5 times larger according to your layout.
 

YESH_23

Member level 4
Joined
Dec 20, 2005
Messages
78
Helped
8
Reputation
16
Reaction score
4
Trophy points
1,288
Location
INDIA
Activity points
1,951
deep n-well purpose

so if we want to connect a different potential than vdd and gnd we can connect it by putting a deep nwell and then taking the source and drain connections
 
  • Like
Reactions: egx

    egx

    Points: 2
    Helpful Answer Positive Rating

vivek rajput

Newbie level 4
Joined
Dec 28, 2005
Messages
6
Helped
7
Reputation
14
Reaction score
7
Trophy points
1,283
Activity points
1,335
deep-nwell

In mixed signal ckts there is only an imaginary line to seperate the Digital and Analog parts.The SUB is common for both ,digital ckts usually operate at higher frequencies so thet switch on and off at very faster rate.They dump minority charge carriers in the SUB which can affect the analog nmos's behaviour.so there is a need to protect analog nMos transistors form this sub noise so there is a concept of Deep N Wells.Plz check the attachment to get the exact picture of Deep N Well..this is not the case with pMOS because we draw p MOS transistors in n Well
 

vijay.kumarreddy

Member level 4
Joined
Jan 6, 2006
Messages
78
Helped
12
Reputation
24
Reaction score
9
Trophy points
1,288
Location
Bangalore,India
Activity points
2,017
deepnwell

Deep N-WELL is a special purpose layer in CMOS process which serves the purpose same as the NLB(N- buried layer in Bipolar process). The purpose is to stop the vertical current coupling generated by the POWER devices to active devices.
 

ccw27

Full Member level 5
Joined
Oct 13, 2004
Messages
267
Helped
14
Reputation
28
Reaction score
6
Trophy points
1,298
Activity points
2,558
deep n-well in mixed signal layout

Is ok for 2 NMOS to share N-Well instead of connecting two N-Wells together by metal? It seems ok to me though ideally connecting them by metal would be closer to the model provided by foundry. Anyone?

Thanks
 

mdcui

Advanced Member level 4
Joined
Aug 23, 2005
Messages
109
Helped
29
Reputation
58
Reaction score
5
Trophy points
1,298
Location
california, USA
Activity points
2,078
psub2 cmos

I'm not sure about other process, but deep N-well device used in flash memory is not for isolation, it is for passing negtive voltage,
you all know that P device can probably be used to pass negtive voltage, but due to its negtive Vt, it is not so effective for this job.
however N device is good at passing small voltage, but the N+ diffusion prevent it from passing negtive voltage, that is how deep -N well device come out, there is another P-well embedded on top of the deep n well and an N device is build in the p-well, so that you can see by applying the P well also negtive voltage, this N device inside it can pass negtive voltage freely and effectively.
we use this kind of device a lot as negtive voltage switch.
 
  • Like
Reactions: garm

    garm

    Points: 2
    Helpful Answer Positive Rating
Joined
Aug 2, 2006
Messages
5
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,281
Location
San Diego CA
Activity points
1,310
what is deep n well

Deep N-well and Deep Trench Isolation (an IBM name) does not really help that much. Deep trench is about 8-10 microns deep, regular n-well about a micron, and the deep n-well structures vary in depth between thos two extremes.

The deep trench isolation in the IBM 5HP Sige process was studied for it's isolation properties pretty thoroughly. (Real silicon, not simulations) and it helped a few db in noise reduction, but that was about it.

That is the reason we launched the 5-HPE process, it was about 6 weeks less time in the foundry, and it brought the wafer cost down a lot as well.

Jerry

www.effectiveelectrons.com

"chips that work"
 

fanbin2000

Newbie level 4
Joined
Apr 20, 2006
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,323
nwell process

Now I am designing a transeiver for mobilevideo, which works at 1.4G. I have tsmc 0.18 models at hand, some are transistors with DNW, but others don't. I don't know which one i should use. anyone knows
 

andy2000a

Advanced Member level 2
Joined
Jul 18, 2001
Messages
597
Helped
14
Reputation
28
Reaction score
8
Trophy points
1,298
Activity points
5,298
what is nwell layer

BJT process moe use deep Nwel device

in gerneal , deep n-well can reduce "substrate coulpe noise " you should check tsmc 0.18um model

by the way , tsmc have nature nmos close 0 Vth
I never use . but why need zero Vth device ?
for RF design or other circuit ?
 

laglead

Full Member level 5
Joined
Feb 21, 2006
Messages
265
Helped
22
Reputation
44
Reaction score
8
Trophy points
1,298
Activity points
2,693
deep-n-well

vivek rajput said:
In mixed signal ckts there is only an imaginary line to seperate the Digital and Analog parts.The SUB is common for both ,digital ckts usually operate at higher frequencies so thet switch on and off at very faster rate.They dump minority charge carriers in the SUB which can affect the analog nmos's behaviour.so there is a need to protect analog nMos transistors form this sub noise so there is a concept of Deep N Wells.Plz check the attachment to get the exact picture of Deep N Well..this is not the case with pMOS because we draw p MOS transistors in n Well

Hi, vivek rajput,
In your post the N-well below P-SUB should be DNW as well. Ion implantation energy is greater for DNW than for NW. Generally DNW is 3um below the surface while NW is 1.5um in UMC process.
 

leelamadhav

Junior Member level 2
Joined
Aug 19, 2006
Messages
22
Helped
2
Reputation
4
Reaction score
0
Trophy points
1,281
Activity points
1,384
what is deep n well

U can use the DNW to place some of the sensitive nmos devices (ofcourse there will be a pwell in the DNW as well)... Here we have an additional degree of freedom to even connect the body of the nmos to the source, hence eliminating the body effect...
 

srivatsan

Full Member level 3
Joined
Aug 4, 2004
Messages
186
Helped
8
Reputation
16
Reaction score
4
Trophy points
1,298
Activity points
2,077
n-well purpose

DNW is used to isolate primairly NMOS from PMOS in vareity of circuits, ranging from digital to analog to RF. It depends.

Usually, you put a DNW and then form a Doughnut shape of NWELL over it and in the "hemisphere" or TUB created by DNW-NWELL is used to create NMOS. Remeber, this helps certain times but sometimes the cap effect is not good. Also now you see parasitic BJT apart from parasitic Diode structures.

In Vivek Rajput's doc, the vertical is NWELL and horizontal is DNW.

Now PSUB2 has been recreated (in many cases) to help LVS pass through rather than for any fab purpose. Other readers put in your though if there are more purposes.

Srivats
 

armixic

Member level 1
Joined
Mar 8, 2006
Messages
39
Helped
4
Reputation
8
Reaction score
1
Trophy points
1,288
Location
U.S.A
Activity points
1,433
deep n well wiki

Besides the isolation provided for reducing the substrate coupling. Also, deep N-well provides a possiblity to tie NMOS body to source with will get rid of body effect.
 

vinoth

Newbie level 2
Joined
Apr 28, 2004
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
10
how to place un nw capa to the deep nwell

Hi friends,

Is anyone have knowledge about the Deep NWELL GR and Deep NWELL Pocket< and how the both techinique will differ interms of LOW and High frequency applicxation.

thanks in advance

Vinoth
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top