In schematic views all you have to go by is the naming
of the master, which is tied to its construction (see the
PDK / device application docs).
In layout views, by inspection - there will be a DNW layer
and for PCells, likely a text that should correspond to the
schematic instance master name.
It's not that NMOS don't benefit from a drivable bulk node,
but that low cost CMOS doesn't provide a separate bulk
connection - rather, a global psub! (P epi and P+ handle,
or actual P bulk uniform silicon in the cheapest cases).
The intervening deep NWell accommodates a less-deep
PWell to house NMOS with Pbody freedom, allow high side
HV MOS / LDMOS and so on.