Decreasing macrocells in the vhdl code

[Abhijith Yadav]

Says it needs 276 macrocells and 176 shareable expanders.... Can u please help me reduce these two to 160 each?

library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.data_packages.all;

entity Viterbi_new is 
port (clock: in std_logic;
	  enc_data: in std_logic_vector(1 downto 0);
	  dec_data: out std_logic_vector(7 downto 0));
end Viterbi_new;

architecture decode of Viterbi_new is
signal metricfinalA,metricfinalB,metricfinalC,metricfinalD: integer range 0 to 30:=1;
signal pathind_A,pathind_B,pathind_C,pathind_D: pathind_data;
signal pathfinalA,pathfinalB,pathfinalC,pathfinalD: std_logic_vector(7 downto 0);
signal ct: integer range 0 to 30:=0;
begin
process(ct,pathind_A,pathind_B,pathind_C,pathind_D,pathfinalA,pathfinalB,pathfinalC,pathfinalD,clock)
begin
if (rising_edge(clock)) then
	ct<=ct+1;
	if(ct>2 and ct<16) then
	pathind_A(0)(7 downto 0)<=pathfinalA(6 downto 0)&'0';
	pathind_A(1)(7 downto 0)<=pathfinalB(6 downto 0)&'0';
	pathind_B(0)(7 downto 0)<=pathfinalC(6 downto 0)&'0';
	pathind_B(1)(7 downto 0)<=pathfinalD(6 downto 0)&'0';
	pathind_C(0)(7 downto 0)<=pathfinalA(6 downto 0)&'1';
	pathind_C(1)(7 downto 0)<=pathfinalB(6 downto 0)&'1';
	pathind_D(0)(7 downto 0)<=pathfinalC(6 downto 0)&'1';
	pathind_D(1)(7 downto 0)<=pathfinalD(6 downto 0)&'1';
	end if;
end if;
end process;

process(metricfinalA,metricfinalB,metricfinalC,metricfinalD,clock,enc_data,ct)
variable outA,outB,outC,outD:xor_data;
variable metricind_A,metricind_B,metricind_C,metricind_D: metricind_data;
variable pathfinal: std_logic_vector(7 downto 0);
variable metric_decide: integer range 0 to 30;
variable metricfinals:metricfinal_data;
variable pathfinals: pathfinal_data;
begin
outA(0):="00";
outA(1):="11";
outB(0):="11";
outB(1):="00";
outC(0):="10";
outC(1):="01";
outD(0):="01";
outD(1):="10";
if(ct>2 and ct<16) then
	if(rising_edge(clock)) then
		for i in 0 to 1 loop
			for j in 0 to 1 loop
				if(outA(i)(j)/=enc_data(j)) then
				metricind_A(i):=metricfinalA+1;
				end if;
				if(outB(i)(j)/=enc_data(j)) then
				metricind_B(i):=metricfinalB+1;
				end if;
				if(outC(i)(j)/=enc_data(j)) then
				metricind_C(i):=metricfinalC+1;
				end if;
				if(outD(i)(j)/=enc_data(j)) then
				metricind_D(i):=metricfinalD+1;
				end if;
			end loop;
		end loop;
		if(metricind_A(0)<metricind_A(1)) then
		metricfinalA<=metricind_A(0);
		metricfinals(0):=metricind_A(0);
		pathfinals(0):=pathind_A(0);
		pathfinalA<=pathind_A(0);
		else
		metricfinalA<=metricind_A(1);
		metricfinals(0):=metricind_A(1);
		pathfinals(0):=pathind_A(1);
		pathfinalA<=pathind_A(1);
		end if;
		if(metricind_B(0)<metricind_B(1)) then
		metricfinalB<=metricind_B(0);
		metricfinals(0):=metricind_B(0);
		pathfinals(1):=pathind_B(0);
		pathfinalB<=pathind_B(0);
		else
		metricfinalB<=metricind_B(1);
		metricfinals(1):=metricind_B(1);
		pathfinals(1):=pathind_B(1);
		pathfinalB<=pathind_B(1);
		end if;
		if(metricind_C(0)<metricind_C(1)) then
		metricfinalC<=metricind_C(0);
		metricfinals(2):=metricind_C(0);
		pathfinals(2):=pathind_C(0);
		pathfinalC<=pathind_C(0);
		else
		metricfinalC<=metricind_C(1);
		metricfinals(2):=metricind_C(1);
		pathfinals(2):=pathind_C(1);
		pathfinalC<=pathind_C(1);
		end if;
		if(metricind_D(0)<metricind_D(1)) then
		metricfinalD<=metricind_D(0);
		metricfinals(3):=metricind_D(0);
		pathfinals(3):=pathind_D(0);
		pathfinalD<=pathind_D(0);
		else
		metricfinalD<=metricind_D(1);
		metricfinals(3):=metricind_D(1);
		pathfinals(3):=pathind_D(1);
		pathfinalD<=pathind_D(1);
		end if;
	pathfinal:=pathfinals(0);
	metric_decide:=metricfinals(0);
	for i in 1 to 3 loop
		if(metricfinals(i)<metric_decide) then
		pathfinal:=pathfinals(i);
		metric_decide:=metricfinals(i);
		end if;
	end loop;
	dec_data<=pathfinal;
	end if; 
end if;
end process;
end decode;
[CODE]

[COLOR="silver"][SIZE=1]- - - Updated - - -[/SIZE][/COLOR]

data_packages

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;

package data_packages is 
type pathfinal_data   is array (3 downto 0) of std_logic_vector(7 downto 0);
type xor_data         is array (1 downto 0) of std_logic_vector(1 downto 0);
type metricind_data   is array (1 downto 0) of integer range 0 to 30;
type metricfinal_data is array (3 downto 0) of integer range 0 to 30;
type pathind_data     is array (1 downto 0) of std_logic_vector(7 downto 0);
end;

 

[TrickyDicky]

What are macrocells and shareable expanders? what chip are you using and what report are you loioking at?

 

[barry]

Just a side-note: your second process uses a gated clock which, unless you need to save power, is a bad idea. It will require extra logic and may cause timing issues. If you can avoid it, it would probably be a good idea; I don't know if will impact your original question, though.

 

[Abhijith Yadav]

dont know what these macrocells are tricky... But im using epm7160slc84-10 from altera....
Barry- ya i changed and merged both the processes... after i posted it here that is(trickydicky, please make note) and changed all the signals to variables...


Any change in your replies? Thanks in advance