Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Decoupling capacitor calculation

Status
Not open for further replies.

malli_1729

Full Member level 5
Joined
Feb 13, 2007
Messages
252
Helped
48
Reputation
96
Reaction score
46
Trophy points
1,308
Location
INDIA
Activity points
3,292
Hi!

we are generally using 0.1uf or o.01uf as decoupling capacitors.

A 0.1uf offers 15.9Ohms to 100K and from 100K as freq increases impedance will decrease still more
So, can we think that it can decouple frequencies from around 100K onwards

A 0.01uf offers 15.9 from 1MHz onwards...

On what basis decoupling is done....

For example if my processor is running at 100Mhz speed whether this clock frequency has any relation with the decoupling capacitor or only the Power supply has effect.


thanking you,

mallikarjun.,k
 

Impedance reaches its minimum at the self-resonant frequency
and then climbs.

Smaller capacitors have higher SRFs generally. I see people
saying that this makes them better than large ones, but this
is not necessarily true; the larger cap might have a lower net
Z than a small one still. Of course a quantity of small ones
providing the equivalent C, would have a much superior
Z@f.

You have to consider what your frequency of interest really
is. If you are trying to run a circuit at 100MHz, that is not the
frequency you care about. You care about keeping the edges
of that clock nicely sharp, which means at least the first few
odd harmonics need to pass through the decoupling without
much loss. Looking at it another way, if you want that 100MHz
clock to spend less than 20% of its time in edge transitions
(10% rise, 40% H, 10% fall, 40% L) then the current pulse
widths are 1nS and the frequency of interest, 1GHz.
Now suddenly
you're quite interested in supply bussing design, number and
length of bonds and leads for supply & ground, etc.
as well as
the capacitor ESL; that is, you don't need to worry whether your
ESL is 0.01nH or 0.1nH if you're feeding the part with a single
VDD bond of 2nH and similar ground (you wouldn't do that, would
you?).

It's not difficult to make a SPICE model of your close-in board
decoupling and package parasitics, apply a pulsed current source
that gives roughly-right dynamic IDD and matches what you
know about internal risetimes, and see what the "chip" (current
source) headroom voltage does. You can get lumped element
model info for decoupling caps fromthe more serious vendors.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top