"Issue", not really, provided that the supply "is what you
think it is". Yes, there's gate ox defect density as a long
term reliability detractor, but it's the same as what you've
got going on already in a CMOS chip design. You only
increase the "size of the target" and eat the odds.
MOSFET Tox is set (you'd like to believe) and process
tuned / cleaned to get "acceptable" gate ox reliability
at max rated supply, up to some design limit of gate ox
area. Now that's all fine, or not, depending on obscured
details like -
- what's "acceptable" for reliability, who says so, and is
-your- customer in agreement?
- do your application-envelope dimensions violate any of
the various precepts that the reliability experiments
analysis took advantage of? Run into this all the time,
trying to make mil/space "HiRel" parts in commercial
pure-play foundries; temp range, supply tolerance,
"other" conditions unanticipated by people in the
nickel-and-dime, throwaway consumer product fab
end of the business.
- Just what is the real gate ox sensitivity to transient
overstress, how high a spike to what voltage in what
duration can be withstood how many times? Because
"2.5V +/- 5% DC" is your "on a good to average day"
reliability supply envelope but supplies have other
behaviors and outside "challenges" that you can only
"put a box around" and tell the customer to respect it
or pound sand. Which doesn't always go over so well,
but it's the industry way (only varying in how much
pain and who gets to taste it).
Integrated capacitors (non-MOS; MIM, MOM, POP) are
always (IME) inferior in capacitance density, trading it
for other interests such as linearity, matching and often
a need to deposit rather than grow the dielectric. They
don't give the areal density you want, and they can't
be "hidden under" low metal levels' local supply routing
(MIM usually sits higher up, MOM is super not-dense,
POP requires dual poly which is uncommon except in
some subset of mixed-signal CMOS flows).