Decouple Cap selection for analog circuit

[zhangz64]

Hi Everyone,

I am trying to understand the how to select decoupling cap effectively.

I see people put a lot of caps at input of their LDO or VDD of Analog IC to filter noise.
Those cap are put in parallel and value ranges from 10uF to 12pF, I understand that those caps are meant to target noise at different frequency since each cap has a different impedence vs Frequency curve, where the minimum impedance sit differently.

Also reduce ESR i think?

My first question is :
Is there a rule of thumb for list of value for those decouple caps ? like, 10uF+1uF + 0.1uF + 1nF ? or Do i need to understand the frequency distribution of the my board?

For example I am using a LDO(lP38511-ADJ) to supply sensitive analog circuit(16 bit DAC) and there is no Switch convertor and high speed bus on the board. the data sheet suggested minimum 10uF. Does it help to put more cap at input to get cleaner output?

or if i want to filter a input to 16 bit DAC that takes 3.3V, that from a LDO what is the normal cap values for decouple ?

My second question is related the cap selection on digikey.

I was design a LDO based on a dev board. (LP38511-ADJ). The dev board used a 10uF as decouple cap which is 1.6 USD by searching its part number

yet i can find a cap with same rating for 0.4 USD. (Same voltage rating, X7R,tolerance).
Is there any other important factors impacting the performance for the cap to justify this price difference?

Also, For 10uF, There are 0805 package and 1206 package for similar price. Does 1206 offer any advantage at all?

Thanks a lot for the help,
Eddy

https://www.digikey.ca/product-detail/en/avx-corporation/1210ZC106KAT2A/478-1625-1-ND/564657

https://www.digikey.ca/product-deta...ca-inc/CL21B106KOQNNNE/1276-2872-1-ND/3890958

 

[KlausST]

Hi,

Some questions you have to answer yourself:
* HOW clean do you want the supply rails?
* What frequency range is the "noise source"?
* How sensible is your circuit at what frequencies?
(Maybe one question is answered in one datasheet, the other in another datasheet. But finally it depends on the curcuit developer to decide how much effort (and cost) he spends in clean supply rails).

*****
As far as I can see your assumptions are correct.
To your questions:
* reduce ESR: yes
* rule of thumb: some use the configuration you wrote. Some use their own knowledge/experience.
* understand frequency dustribution: For me this is the better way. A bulk capacitor to suvive short time of power loss. Capacitors at each IC according datasheet (here is where the frequency dustribution counts). And then decide the pieces of circuit where you think they need "special care". (Extra LC, RC, GND plane splits...)
* Add more capacitor: It will reduce ripple. But if this further improves overall performance is another question...
* filter for 16 bit DAC: you should find this in the DAC datasheet. Maybe given as PSRR value or PSRR chart. For high sensitive devices (like high resolution DACs or ADCs) I recommend to use individually RC or LC filtered supply rails. It will be more easy and more effective to filter a small power supply section than the whole common board supply.
* Cap selection / digikey: The datasheet recommendation is as old as the datasheet itself. But progress in capacitor development goes on. This means the price of capacitors will change with time. And there will be new technologies for producing capacitors: reducing price and improve specifications. My recommendation: Find your own capacitor with the specifications given in the datasheet. Check your stock.
* capacitor performance: you need to read the datasheet of the device where you need the capacitor. Often one wants ESR to be as low as can be, but some devices are not stable with extremely low ESR. Check: voltage rating, ripple current rating, ESR, resonant frequency,..
* 0805 vs 1206: I assume 0805 is just the more modern technology. But in detail you have to compare datasheets.

(Btw: how did you manage EAGLE to draw a schematic without automatically setting the junction dots?
This usually is extra effort. Does it make sense? At least it makes it impossible for us to see what lines are joined and what are crossings only.)

Klaus

 

[Airbag79]

Hi,

Some questions you have to answer yourself:
* HOW clean do you want the supply rails?
* What frequency range is the "noise source"?
* How sensible is your circuit at what frequencies?
(Maybe one question is answered in one datasheet, the other in another datasheet. But finally it depends on the curcuit developer to decide how much effort (and cost) he spends in clean supply rails).

*****
As far as I can see your assumptions are correct.
To your questions:
* reduce ESR: yes
* rule of thumb: some use the configuration you wrote. Some use their own knowledge/experience.
* understand frequency dustribution: For me this is the better way. A bulk capacitor to suvive short time of power loss. Capacitors at each IC according datasheet (here is where the frequency distribution counts). And then decide the pieces of circuit where you think they need "special care". (Extra LC, RC, GND plane splits...)
* Add more capacitor: It will reduce ripple. But if this further improves overall performance is another question...
* filter for 16 bit DAC: you should find this in the DAC datasheet. Maybe given as PSRR value or PSRR chart. For high sensitive devices (like high resolution DACs or ADCs) I recommend to use individually RC or LC filtered supply rails. It will be more easy and more effective to filter a small power supply section than the whole common board supply.
* Cap selection / digikey: The datasheet recommendation is as old as the datasheet itself. But progress in capacitor development goes on. This means the price of capacitors will change with time. And there will be new technologies for producing capacitors: reducing price and improve specifications. My recommendation: Find your own capacitor with the specifications given in the datasheet. Check your stock.
* capacitor performance: you need to read the datasheet of the device where you need the capacitor. Often one wants ESR to be as low as can be, but some devices are not stable with extremely low ESR. Check: voltage rating, ripple current rating, ESR, resonant frequency,..
* 0805 vs 1206: I assume 0805 is just the more modern technology. But in detail you have to compare datasheets.

(Btw: how did you manage EAGLE to draw a schematic without automatically setting the junction dots?
This usually is extra effort. Does it make sense? At least it makes it impossible for us to see what lines are joined and what are crossings only.)

Klaus

Actually, wrt ESR and PDN/Z impedance you typically want more ESR to quench any modal peaks that exist in your frequency band. The R dampens/flattens the magnitude of the modal peak to bring down the PDN impedance at that frequency.

OP:

You really need to perform a PDN analysis in the frequency domain (Z parameters). You can do this by extracting the SYZ parameters. The limiting factor is inductance, capacitance has very little to do with a solid PDN design wrt AC currents. The capacitance values are intrinsic to frequency bands. You also need to calculate a Target Impedance for the PDN/Power form of interest. Zt = [(Allowable ripple %)*(The voltage of the power form)/(max di/dt)]. Typically your target impedance will be in the milliohm realm.

Every decoupling component has a frequency limit of operation. VRM = DC-Switching frequency. Bulk Capacitors from VRM switching up to ~1 MHz. SMT/ceramics can get you up to the hundreds of MHz. Package caps/On-die caps up to GHz realm. As well as inter-plane capacitance (pwr/gnd vertical spacing, the closer the higher the inter-plane capacitance, attacks GHz modal peaks)The key is understanding what you target impedance is, and what the frequency band of interest is. Capacitance has very little to do with it. PDN performance is limited by the loop inductance.

Determine the max di/dt switching current. Determine the frequency band you need to meet the target impedance over. Measure the loop inductance of each discrete capacitor (including ESL + Mounting Inductance). Perform Z frequency domain analysis. X,Y location of caps is second order effect due to spreading inductance. Z/vertical inductance is the first-order limiting factor.

 

[zhangz64]

The key is understanding what you target impedance is, and what the frequency band of interest is. Capacitance has very little to do with it. PDN performance is limited by the loop inductance.

i think this kind makes sense to me.

Let us say i am designing a board with USB 5V as input source. I want to filter it out. How do i know the frequency of interests?

Also, I have a 24Mhz uController on the board. Then does the noise are mostly 24Mhz switching noise?(provide if there is no there noise source on board)

Thanks,
Eddy

 

[KlausST]

Hi,

Are you really interested in the 24MHz? I'd say: No.
If you build an audio device, for example, then you are interested in audio frequency.

You can filter away all other frequencies....24MHz automatically is filtered away.

But for sure it is good to know about the 24MHz. If this is the source of noise, then you can focus on that.
But every clock frequency has it's overtones. And in the case of microcontroller clock it has integer divisions of the clock, caused by the software...

Klaus