Decoding DCF Signal using FPGA Spartan VHDL

[Raj Sohal]

I am in the process of writing a code to decode the DCF signal. I keep getting an error

WARNING:Xst:2935 - Signal 'year<3>', unconnected in block 'dcf_decode', is tied to its initial value (0010).
WARNING:Xst:2935 - Signal 'year<2>', unconnected in block 'dcf_decode', is tied to its initial value (0000).

I am unsure how to solve this as it simulates fine and outputs the correct graph, but the synthesizing gives this error.

Here is my code below, it is long. Any help would be greatly appreciated.

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
library IEEE;
 
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use WORK.util.all;
 
entity dcf_decode is
 
    generic
    (
        clk_freq:   positive := 125000000; -- Hz
        gate_delay: time     := 1 ns
    );
 
    port
    (
        rst:    in  std_logic                    := 'X'; -- reset
        clk:    in  std_logic                    := 'X'; -- clock
        
        si:     in  std_logic                    := 'X'; -- start of second in
        mi:     in  std_logic                    := 'X'; -- start of minute in
        bi:     in  std_logic                    := 'X'; -- bit in
        year:   out bcd_digit_vector(3 downto 0) := (3 => bcd_two, 2 => bcd_zero, others => bcd_minus);
        month:  out bcd_digit_vector(1 downto 0) := (others => bcd_minus);
        day:    out bcd_digit_vector(1 downto 0) := (others => bcd_minus);
        hour:   out bcd_digit_vector(1 downto 0) := (others => bcd_minus);
        minute: out bcd_digit_vector(1 downto 0) := (others => bcd_minus);
        second: out bcd_digit_vector(1 downto 0) := (others => bcd_zero);  
        tr:     out std_logic                    := '0'  -- new bit trigger
    );
 
end dcf_decode;
 
architecture rtl of dcf_decode is
 
    type states is (start,data_out,hold_delay,trig_rst);
    constant one_min : natural := 60;
    signal state: states := start;
    signal nxt_state: states := start;
    signal output: bcd_digit_vector(9 downto 0) := (others=> bcd_minus);            -- Avoid latching
    signal output_nxt: bcd_digit_vector(9 downto 0) := (others=> bcd_minus);    
    signal sec_unit: unsigned((n_bits(9) - 1 ) downto 0) := (others => '0');        -- Seconds units
    signal sec_tenth: unsigned((n_bits(9) - 1 ) downto 0) := (others => '0');       -- Seconds tenth
    signal sec_unit_nxt: unsigned((n_bits(9) - 1 ) downto 0) := (others => '0');
    signal sec_tenth_nxt: unsigned((n_bits(9) - 1 ) downto 0) := (others => '0');
    signal cnt : unsigned((n_bits(one_min) - 1) downto 0) := (others => '0');       -- Declare a counter to populate array
    signal nxt_cnt : unsigned((n_bits(one_min) -1) downto 0) := (others => '0');        -- Next counter 
    signal bit_array : unsigned(59 downto 0) := (others => 'X');                -- Array to store values
    signal bit_array_nxt: unsigned(59 downto 0) := (others => 'X');             -- Array to store values
    shared variable x: integer := 0;                            -- Counter
    shared variable nxt_x: integer := 0;
 
begin
 
    process (rst, clk)
        begin
          if (rst = '1') then
        cnt <= (others => '0');
        state <= start;
 
          elsif clk'event and (clk = '1') then
        cnt <= nxt_cnt;
            state <= nxt_state;
        sec_unit<= sec_unit_nxt;
        sec_tenth <= sec_tenth_nxt;
        bit_array <= bit_array_nxt;
        output <= output_nxt;
        x  := nxt_x;
        
          end if;
    end process; 
  
    process(si,mi,bi,cnt,state, bit_array, sec_unit,sec_tenth,output)
    begin
        nxt_cnt <= cnt;
            nxt_state <= state;
        tr <= '0';                      -- Reset the bit trigger after every clock cycle
        sec_tenth_nxt <= sec_tenth;
        sec_unit_nxt <= sec_unit;
        bit_array_nxt <= bit_array;
        output_nxt<= output;
        nxt_x := x;
 
case state is
 
    when start =>                           -- Waiting to recieve a second pulse
        bit_array_nxt(x) <= bi;
                if(si = '1' and mi = '0') then              -- Second input high and min input high
            if(sec_unit < 9) then
            sec_unit_nxt <= sec_unit + 1;
            else
            sec_unit_nxt <= (others => '0');
            sec_tenth_nxt <= sec_tenth + 1;
            end if;
            nxt_x := x + 1;
            nxt_state <= hold_delay;
        elsif(si = '1' and mi = '1') then           -- Second input high and min input high
                nxt_state <= hold_delay;            -- Go state three
                sec_tenth_nxt <= (others => '0');   -- Reset
                sec_unit_nxt <= (others => '0');    -- Reset
                nxt_x := 0;
            elsif (x = 59) then             -- When counter equal 59
                nxt_state <= data_out;          -- Go state 2
                        end if;
 
    when data_out =>    
        if (sec_unit=9 and sec_tenth=5) then
 
        if((bit_array(28) xor bit_array(27) xor bit_array(26) xor bit_array(25) xor bit_array(24) xor bit_array(23) xor bit_array(22) xor bit_array(21)) = '0') then --Parity check for min
        output_nxt(0) <= bit_array(24) & bit_array(23) & bit_array(22) & bit_array(21);     -- Unit min value           
        output_nxt(1) <= '0' & bit_array(27) & bit_array(26) & bit_array(25);           -- Tenth min value
        else 
        output_nxt(0) <=  bcd_error;
        output_nxt(1) <=  bcd_error;
        end if;
    
        if((bit_array(35) xor bit_array(34) xor bit_array(33) xor bit_array(32) xor bit_array(31) xor bit_array(30) xor bit_array(29)) = '0') then      --Parity check for hour
        output_nxt(2) <= bit_array(32) & bit_array (31) & bit_array(30) & bit_array(29);    -- Unit hour value
        output_nxt(3) <= "00" & bit_array(34) & bit_array(33);                  -- Tenth hour value
        else 
        output_nxt(2) <= bcd_error;
        output_nxt(3) <= bcd_error;
        end if;
 
        if((bit_array(58) xor bit_array(57) xor bit_array(56) xor bit_array(55) xor bit_array(54) xor bit_array(53) xor bit_array(52) xor bit_array(51) xor bit_array(50) 
        xor bit_array(49) xor bit_array(48) xor bit_array(47) xor bit_array(46) xor bit_array(45) xor bit_array(44) xor bit_array(43) xor bit_array(42) xor bit_array(41) 
        xor bit_array(40) xor bit_array(39) xor bit_array(38) xor bit_array(37) xor bit_array(36)) = '0') then                          --Parity check for date
        output_nxt(4) <= bit_array(39) & bit_array(38) & bit_array(37) & bit_array(36);     
        output_nxt(5) <= "00" & bit_array(41) & bit_array(40);                  
        output_nxt(6) <= bit_array(48) & bit_array(47) & bit_array(46) & bit_array(45);             
        output_nxt(7) <= "000" & bit_array(49);
        output_nxt(8) <= bit_array(53) & bit_array(52) & bit_array(51) & bit_array(50); 
        output_nxt(9) <= bit_array(57) & bit_array(56) & bit_array(55) & bit_array(54);
        else 
        output_nxt(4) <= bcd_error;
        output_nxt(5) <= bcd_error;
        output_nxt(6) <= bcd_error;
        output_nxt(7) <= bcd_error;
        output_nxt(8) <= bcd_error;
        output_nxt(9) <= bcd_error;
        end if;
 
        sec_tenth_nxt <= (others => '0'); 
        sec_unit_nxt <= (others => '0');
        nxt_x := 0;
                nxt_state <= start;
 
        
        else
        sec_tenth_nxt <= (others => '0'); 
        sec_unit_nxt <= (others => '0');
        nxt_x := 0;
                nxt_state <= start;                 -- Switch the state back to start
 
        end if;
 
    when hold_delay => nxt_state <= trig_rst;
 
    when trig_rst =>tr <= '1';
            nxt_state <= start;
 
                    
       end case;
  end process;
second(0) <= sec_unit;
second(1) <= sec_tenth;
 
minute(0) <= output(0);
minute(1) <= output(1);
 
hour(0)   <= output(2);
hour(1)   <= output(3);
 
day(0)  <= output(4);
day(1)  <= output(5);
 
month(0) <= output(6);
month(1) <= output(7);
 
year(0) <= output(8);
year(1) <= output(9);
 
end rtl;

---

 

[mrflibble]

It's not an error. It's a warning. And it warns you that you have some unconnected signals. Usually this sort of warning is not a problem, but always good to check so you know if it is behaving properly. For related info you can always google the error/warning code, Xst:2935 in this case.