shaiko
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In VHDL 2008
Is it possible to declare an unconsrained unsigned variable in a function?
For example:
Is it possible to declare an unconsrained unsigned variable in a function?
For example:
Code:
function some_function ( x : unsigned ; y : unsigned ) return unsigned is
variable result : unsigned ; -- "result" is defined as an unconstrained unsigned.
begin
if x > y then
result := x ; -- "result" gets constrained according to the size of x
else
result := y ; -- "result" gets constrained according to the size of y
end if ;
return result ;
end function some_function ;