declaring a constant value for all modules in verilog

Status
Not open for further replies.
D

dipin

Full Member level 4
Joined
Jul 16, 2014
Messages
223
Helped
14
Reputation
28
Reaction score
14
Trophy points
18
Activity points
1,731
hi,
i had some 40 nos of 32 bit constant in a verilog module used for some calculations. i am replicating this module for some 10 times.
so basically i am repeating the values in all the modules and wasting resources. so is it possible to declare it only once and use it in all the 10 modules.
10 instantiations are from the same module.

i declared it like this.
reg [15:0] mem [0:40];
Click to expand...
so instead of repeating like this in all modules is it possible to declare only once and use it in all the 10 modules?

how can i do it? if it do so will it reduce the logic utilization?

any help is really appriciated

thanks and regards
 

Constants known at synthesis time are inserted in each expression separately. The definition method doesn't affect the logic or memory utilization. It's only a question of effective code writing.

In the System Verilog world, packages are a suitable way to define global constants (as in VHDL since ever).

In plain Verilog, including constant definitions is probably the best way.
 
Reactions: dipin

    D

    dipin

    Points: 2
    Helpful Answer Positive Rating
hi,
so if i use some compiler directive like `include (or some other way)and include all of my constants,

it won't help me to reduce my logic utilization right?
while elaborating, it will assigned in each module separately ... is it?

thanks
 

Yes. There are however some cases where array constants can be more effectively implemented as initialized block ram, e.g. when multiple constants are muxed to a single target.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…