Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 subtype t_dim1 is signed; type t_dim1_vector is array (natural range <>) of t_dim1; type t_dim2_vector is array (natural range <>) of t_dim1_vector; constant c_mult : t_rom_vector2 := c_dct2_b2 when (g_bl_size = 2 and g_tr_type = 0) else c_dct2_b4 when (g_bl_size = 4 and g_tr_type = 0) else c_dct2_b8 when (g_bl_size = 8 and g_tr_type = 0) else c_dct2_b16 when (g_bl_size = 16 and g_tr_type = 0) else c_dct2_b32 when (g_bl_size = 32 and g_tr_type = 0) else c_dct2_b64 when (g_bl_size = 64 and g_tr_type = 0) else c_dct8_b4 when (g_bl_size = 4 and g_tr_type = 1) else c_dct8_b8 when (g_bl_size = 8 and g_tr_type = 1) else c_dct8_b16 when (g_bl_size = 16 and g_tr_type = 1) else c_dct8_b32 when (g_bl_size = 32 and g_tr_type = 1) else c_dst7_b4 when (g_bl_size = 4 and g_tr_type = 2) else c_dst7_b8 when (g_bl_size = 8 and g_tr_type = 2) else c_dst7_b16 when (g_bl_size = 16 and g_tr_type = 2) else c_dst7_b32 when (g_bl_size = 32 and g_tr_type = 2);
Code VHDL - [expand] 1 2 3 4 5 type t_rom_vector3 is array (natural range <>) of t_rom_vector2; constant c_trtype_blsz : t_rom_vector3 := ( (c_dct2_b2, c_dct2_b4, c_dct2_b8, c_dct2_b16, c_dct2_b32, c_dct2_b64), (c_zero, c_dct8_b4, c_dct8_b8, c_dct8_b16, c_dct8_b32, c_zero), (c_zero, c_dst7_b4, c_dst7_b8, c_dst7_b16, c_dst7_b32, c_zero) );
So is there a way of generating a generic code for this?(82) At depth 2, array length is 6; aggregate length is 126
(83) At depth 2, array length is 6; aggregate length is 64
(84) At depth 2, array length is 6; aggregate length is 64
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pkg_TrCoeffMatrix is
-- subtype t_dim1_sulv is std_ulogic_vector;
-- type t_dim1_vector_sulv is array (natural range <>) of t_dim1_sulv;
-- type t_dim2_vector_sulv is array (natural range <>) of t_dim1_vector_sulv;
-- type t_dim3_vector_sulv is array (natural range <>) of t_dim2_vector_sulv;
subtype t_rom2 is integer;
type t_rom_vector1 is array (natural range <>) of t_rom2;
type t_rom_vector2 is array (natural range <>) of t_rom_vector1;
type t_rom_vector3 is array (natural range <>) of t_rom_vector2;
-- dct2 coeff matrix
constant c_zero : t_rom_vector2 (0 to 1)(0 to 1)
:=( (0,0),
(0,0) );
constant c_dct2_b2 : t_rom_vector2 (0 to 1)(0 to 1)
:=( (64,64),
(64,-64) );
constant c_dct2_b4 : t_rom_vector2 (0 to 3)(0 to 3)
:=( (64, 64, 64, 64),
(83, 36, -36, -83),
(64, -64, -64, 64),
(36, -83, 83, -36) );
constant c_dct2_b8 : t_rom_vector2 (0 to 7)(0 to 7)
:=( (64, 64, 64, 64, 64, 64, 64, 64), ( 89, 75, 50, 18, -18, -50, -75, -89), ( 83, 36, -36, -83, -83, -36, 36, 83), ( 75, -18, -89, -50, 50, 89, 18, -75), ( 64, -64, -64, 64, 64, -64, -64, 64), ( 50, -89, 18, 75, -75, -18, 89, -50), ( 36, -83, 83, -36, -36, 83, -83, 36), ( 18, -50, 75, -89, 89, -75, 50, -18) );
constant c_trtype_blsz : t_rom_vector3 := ( (c_dct2_b2, c_dct2_b4, c_dct2_b8, c_dct2_b16, c_dct2_b32, c_dct2_b64),
(c_zero, c_dct8_b4, c_dct8_b8, c_dct8_b16, c_dct8_b32, c_zero),
(c_zero, c_dst7_b4, c_dst7_b8, c_dst7_b16, c_dst7_b32, c_zero) );
end pkg_TrCoeffMatrix;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library vvc_lib;
use vvc_lib.pkg_TrCoeffMatrix.all;
entity generic_multiplier is
generic (
g_coeff_width : natural := 16;
g_bl_size : natural := 4;
g_bl_type : natural := 1; --(0,1,2,3,4,5)--> bl_sz(2,4,8,16,32,64)
g_tr_type : natural := 0 -- 0--> DCT2, 1--> DCT8, 2--> DST7
);
port (
i_data : in std_ulogic_vector(g_bl_size*g_bl_size*g_coeff_width-1 downto 0); -- (M--> L)SB <= (|Pix_N|...|Pix_2|Pix1|) in memory
o_data : out std_ulogic_vector(2*g_bl_size*g_bl_size*g_bl_size*g_coeff_width-1 downto 0)
);
end entity generic_multiplier;
architecture rtl of generic_multiplier is
subtype t_dim1 is signed;
type t_dim1_vector is array (natural range <>) of t_dim1;
type t_dim2_vector is array (natural range <>) of t_dim1_vector;
signal s_data_in : t_dim2_vector (0 to g_bl_size-1)(0 to g_bl_size-1)(g_coeff_width-1 downto 0);
signal s_data_out : signed(2*g_bl_size*g_bl_size*g_bl_size*g_coeff_width-1 downto 0) := (others => '0');
constant c_mult : t_rom_vector3 := c_trtype_trblsz(0 to 3)(0 to 5)(g_tr_type)(g_bl_type);
As now it is clear g_xyz is generic constant. The errors at 82,83 and 84 come from the following lines of code:what is g_bl_size? Is it a constant? What about g_tr_type? You also haven't covered every possible case in your when statement. You also haven't shown us the part of the code that generates the error or associated line numbers.
constant c_trtype_blsz : t_rom_vector3 := ( (c_dct2_b2, c_dct2_b4, c_dct2_b8, c_dct2_b16, c_dct2_b32, c_dct2_b64),
(c_zero, c_dct8_b4, c_dct8_b8, c_dct8_b16, c_dct8_b32, c_zero),
(c_zero, c_dst7_b4, c_dst7_b8, c_dst7_b16, c_dst7_b32, c_zero) );
It simply means that the prefix g_ is a generic. You had asked for multiple keywords with prefix g_. Moreover, you can refer to the code to get answer to your primary question.It is most certainly NOT "clear g_xyz is generic constant". Nowhere does g_xyz appear in your code.
I am trying to use a constant in a generic way. Please refer to the original question in thread #1. I am trying to make a constant c_mult, whose values could be c_dct2_b2 or c_dct2_b4 or something else as per their location in the c_mult constant.Further, your statement:
constant c_trtype_blsz : t_rom_vector3 := ( (c_dct2_b2,...
references things that don't appear anywhere (c_dct2_b2, e.g.).
c_mult chooses between constants of different sizes. I synthesized this but it seems that it is not simulatable...
The package is as follows:@rafimiet
Im not fully convinced by your arguments:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pkg_TrCoeffMatrix is
subtype t_rom2 is integer;
type t_rom_vector1 is array (natural range <>) of t_rom2;
type t_rom_vector2 is array (natural range <>) of t_rom_vector1;
constant c_dct2_b2 : t_rom_vector2 (0 to 1)(0 to 1)
:=( (64,64),
(64,-64) );
constant c_dct2_b4 : t_rom_vector2 (0 to 3)(0 to 3)
:=( (64, 64, 64, 64),
(83, 36, -36, -83),
(64, -64, -64, 64),
(36, -83, 83, -36) );
constant c_dct2_b8 : t_rom_vector2 (0 to 7)(0 to 7)
:=( (64, 64, 64, 64, 64, 64, 64, 64), ( 89, 75, 50, 18, -18, -50, -75, -89), ( 83, 36, -36, -83, -83, -36, 36, 83), ( 75, -18, -89, -50, 50, 89, 18, -75), ( 64, -64, -64, 64, 64, -64, -64, 64), ( 50, -89, 18, 75, -75, -18, 89, -50), ( 36, -83, 83, -36, -36, 83, -83, 36), ( 18, -50, 75, -89, 89, -75, 50, -18) );
constant c_dct2_b16 : t_rom_vector2 (0 to 15)(0 to 15)
:=( ( 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64), ( 90, 87, 80, 70, 57, 43, 25, 9, -9, -25, -43, -57, -70, -80, -87, -90), ( 89, 75, 50, 18, -18, -50, -75, -89, -89, -75, -50, -18, 18, 50, 75, 89), ( 87, 57, 9, -43, -80, -90, -70, -25, 25, 70, 90, 80, 43, -9, -57, -87), ( 83, 36, -36, -83, -83, -36, 36, 83, 83, 36, -36, -83, -83, -36, 36, 83), ( 80, 9, -70, -87, -25, 57, 90, 43, -43, -90, -57, 25, 87, 70, -9, -80), ( 75, -18, -89, -50, 50, 89, 18, -75, -75, 18, 89, 50, -50, -89, -18, 75), ( 70, -43, -87, 9, 90, 25, -80, -57, 57, 80, -25, -90, -9, 87, 43, -70), ( 64, -64, -64, 64, 64, -64, -64, 64, 64, -64, -64, 64, 64, -64, -64, 64), ( 57, -80, -25, 90, -9, -87, 43, 70, -70, -43, 87, 9, -90, 25, 80, -57), ( 50, -89, 18, 75, -75, -18, 89, -50, -50, 89, -18, -75, 75, 18, -89, 50), ( 43, -90, 57, 25, -87, 70, 9, -80, 80, -9, -70, 87, -25, -57, 90, -43), ( 36, -83, 83, -36, -36, 83, -83, 36, 36, -83, 83, -36, -36, 83, -83, 36), ( 25, -70, 90, -80, 43, 9, -57, 87, -87, 57, -9, -43, 80, -90, 70, -25), ( 18, -50, 75, -89, 89, -75, 50, -18, -18, 50, -75, 89, -89, 75, -50, 18), ( 9, -25, 43, -57, 70, -80, 87, -90, 90, -87, 80, -70, 57, -43, 25, -9));
constant c_dct8_b4 : t_rom_vector2 (0 to 3)(0 to 3)
:=( ( 84, 74, 55, 29), ( 74, 0, -74, -74), ( 55, -74, -29, 84), ( 29, -74, 84, -55));
constant c_dct8_b8 : t_rom_vector2 (0 to 7)(0 to 7)
:=( ( 86, 85, 78, 71, 60, 46, 32, 17), ( 85, 60, 17, -32, -71, -86, -78, -46), ( 78, 17, -60, -86, -46, 32, 85, 71), ( 71, -32, -86, -17, 78, 60, -46, -85), ( 60, -71, -46, 78, 32, -85, -17, 86), ( 46, -86, 32, 60, -85, 17, 71, -78), ( 32, -78, 85, -46, -17, 71, -86, 60), ( 17, -46, 71, -85, 86, -78, 60, -32));
constant c_dct8_b16 : t_rom_vector2 (0 to 15)(0 to 15)
:=( ( 88, 88, 87, 85, 81, 77, 73, 68, 62, 55, 48, 40, 33, 25, 17, 8), ( 88, 81, 68, 48, 25, 0, -25, -48, -68, -81, -88, -88, -81, -68, -48, -25), ( 87, 68, 33, -8, -48, -77, -88, -81, -55, -17, 25, 62, 85, 88, 73, 40), ( 85, 48, -8, -62, -88, -77, -33, 25, 73, 88, 68, 17, -40, -81, -87, -55), ( 81, 25, -48, -88, -68, 0, 68, 88, 48, -25, -81, -81, -25, 48, 88, 68), ( 77, 0, -77, -77, 0, 77, 77, 0, -77, -77, 0, 77, 77, 0, -77, -77), ( 73, -25, -88, -33, 68, 77, -17, -88, -40, 62, 81, -8, -87, -48, 55, 85), ( 68, -48, -81, 25, 88, 0, -88, -25, 81, 48, -68, -68, 48, 81, -25, -88), ( 62, -68, -55, 73, 48, -77, -40, 81, 33, -85, -25, 87, 17, -88, -8, 88), ( 55, -81, -17, 88, -25, -77, 62, 48, -85, -8, 88, -33, -73, 68, 40, -87), ( 48, -88, 25, 68, -81, 0, 81, -68, -25, 88, -48, -48, 88, -25, -68, 81), ( 40, -88, 62, 17, -81, 77, -8, -68, 87, -33, -48, 88, -55, -25, 85, -73), ( 33, -81, 85, -40, -25, 77, -87, 48, 17, -73, 88, -55, -8, 68, -88, 62), ( 25, -68, 88, -81, 48, 0, -48, 81, -88, 68, -25, -25, 68, -88, 81, -48), ( 17, -48, 73, -87, 88, -77, 55, -25, -8, 40, -68, 85, -88, 81, -62, 33), ( 8, -25, 40, -55, 68, -77, 85, -88, 88, -87, 81, -73, 62, -48, 33, -17) );
constant c_dst7_b4 : t_rom_vector2 (0 to 3)(0 to 3)
:=( ( 29, 55, 74, 84 ), ( 74, 74, 0, -74 ), ( 84, -29, -74, 55 ), ( 55, -84, 74, -29 ));
constant c_dst7_b8 : t_rom_vector2 (0 to 7)(0 to 7)
:=( ( 17, 32, 46, 60, 71, 78, 85, 86), ( 46, 78, 86, 71, 32, -17, -60, -85), ( 71, 85, 32, -46, -86, -60, 17, 78), ( 85, 46, -60, -78, 17, 86, 32, -71), ( 86, -17, -85, 32, 78, -46, -71, 60), ( 78, -71, -17, 85, -60, -32, 86, -46), ( 60, -86, 71, -17, -46, 85, -78, 32), ( 32, -60, 78, -86, 85, -71, 46, -17));
constant c_dst7_b16 : t_rom_vector2 (0 to 15)(0 to 15)
:=( ( 8, 17, 25, 33, 40, 48, 55, 62, 68, 73, 77, 81, 85, 87, 88, 88), ( 25, 48, 68, 81, 88, 88, 81, 68, 48, 25, 0, -25, -48, -68, -81, -88), ( 40, 73, 88, 85, 62, 25, -17, -55, -81, -88, -77, -48, -8, 33, 68, 87), ( 55, 87, 81, 40, -17, -68, -88, -73, -25, 33, 77, 88, 62, 8, -48, -85), ( 68, 88, 48, -25, -81, -81, -25, 48, 88, 68, 0, -68, -88, -48, 25, 81), ( 77, 77, 0, -77, -77, 0, 77, 77, 0, -77, -77, 0, 77, 77, 0, -77), ( 85, 55, -48, -87, -8, 81, 62, -40, -88, -17, 77, 68, -33, -88, -25, 73), ( 88, 25, -81, -48, 68, 68, -48, -81, 25, 88, 0, -88, -25, 81, 48, -68), ( 88, -8, -88, 17, 87, -25, -85, 33, 81, -40, -77, 48, 73, -55, -68, 62), ( 87, -40, -68, 73, 33, -88, 8, 85, -48, -62, 77, 25, -88, 17, 81, -55), ( 81, -68, -25, 88, -48, -48, 88, -25, -68, 81, 0, -81, 68, 25, -88, 48), ( 73, -85, 25, 55, -88, 48, 33, -87, 68, 8, -77, 81, -17, -62, 88, -40), ( 62, -88, 68, -8, -55, 88, -73, 17, 48, -87, 77, -25, -40, 85, -81, 33), ( 48, -81, 88, -68, 25, 25, -68, 88, -81, 48, 0, -48, 81, -88, 68, -25), ( 33, -62, 81, -88, 85, -68, 40, -8, -25, 55, -77, 88, -87, 73, -48, 17), ( 17, -33, 48, -62, 73, -81, 87, -88, 88, -85, 77, -68, 55, -40, 25, -8));
end pkg_TrCoeffMatrix;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library vvc_lib;
use vvc_lib.pkg_TrCoeffMatrix.all;
entity generic_multiplier is
generic (
g_coeff_width : natural := 4;
g_bl_size : natural := 4;
-- g_bl_type : natural := 1; --(0,1,2,3,4,5)--> bl_sz(2,4,8,16,32,64)
g_tr_type : natural := 0 -- 0--> DCT2, 1--> DCT8, 2--> DST7
);
port (
i_data : in std_ulogic_vector(g_bl_size*g_bl_size*g_coeff_width-1 downto 0); -- (M--> L)SB <= (|Pix_N|...|Pix_2|Pix1|) in memory
o_data : out std_ulogic_vector(2*g_bl_size*g_bl_size*g_bl_size*g_coeff_width-1 downto 0)
);
end entity generic_multiplier;
architecture rtl of generic_multiplier is
subtype t_dim1 is signed;
type t_dim1_vector is array (natural range <>) of t_dim1;
type t_dim2_vector is array (natural range <>) of t_dim1_vector;
-- type t_dim2_vector is array (0 to 3, 0 to 7) of std_ulogic_vector(7 downto 0);
signal s_data_in : t_dim2_vector (0 to g_bl_size-1)(0 to g_bl_size-1)(g_coeff_width-1 downto 0);
signal s_data_out : signed(2*g_bl_size*g_bl_size*g_bl_size*g_coeff_width-1 downto 0) := (others => '0');
--constant c_mult : t_rom_vector2 := c_dct2_b4;
-- The following is synthesizable but not simulatable
constant c_mult : t_rom_vector2 := c_dct2_b2 when (g_bl_size = 2 and g_tr_type = 0) else
c_dct2_b4 when (g_bl_size = 4 and g_tr_type = 0) else
c_dct2_b8 when (g_bl_size = 8 and g_tr_type = 0) else
c_dct2_b16 when (g_bl_size = 16 and g_tr_type = 0) else
c_dct8_b4 when (g_bl_size = 4 and g_tr_type = 1) else
c_dct8_b8 when (g_bl_size = 8 and g_tr_type = 1) else
c_dct8_b16 when (g_bl_size = 16 and g_tr_type = 1) else
c_dst7_b4 when (g_bl_size = 4 and g_tr_type = 2) else
c_dst7_b8 when (g_bl_size = 8 and g_tr_type = 2) else
c_dst7_b16 when (g_bl_size = 16 and g_tr_type = 2);
begin
-- Reshape input data -- No need to change upto 4x4 block
gen00: for i in 0 to g_bl_size-1 generate
gen01: for j in 0 to g_bl_size-1 generate
s_data_in(i)(j) <= signed(i_data(g_coeff_width*(i*g_bl_size+j+1)-1 downto g_coeff_width*(i*g_bl_size+j)));
end generate gen01;
end generate gen00;
-- Matrix Multiplication
gen02: for i in 0 to g_bl_size-1 generate
gen03: for j in 0 to g_bl_size-1 generate
gen04: for k in 0 to g_bl_size-1 generate
s_data_out(2*g_coeff_width*(i*g_bl_size*g_bl_size+j*g_bl_size+k+1)-1 downto 2*g_coeff_width*(i*g_bl_size*g_bl_size+j*g_bl_size+k)) <= s_data_in(i)(k) * c_mult(k)(j);
end generate gen04;
end generate gen03;
end generate gen02;
-- Output Multiplications g_bl_size**3 (in number) and 2*g_coeff_width (each)
o_data(g_bl_size*g_bl_size*g_bl_size*2*g_coeff_width-1 downto 0) <= std_ulogic_vector(s_data_out(g_bl_size*g_bl_size*g_bl_size*2*g_coeff_width-1 downto 0));
end architecture rtl;
Please enlighten me, that is why I am asking hereYou are missing several type declarations in your code postings. Please show the whole code.
So, in general, I think you have a misunderstanding of how VHDL arrays work.
As seen in the thread #7, pkg_TrCoeffMatrix.vhd consist of multiple constants. These constants are used as one of the two inputs for matrix multiplications. Now as matrix sizes changes, so does the size of these constants. We need to choose an appropriate constant.So what Im trying to understand now is what the problem actually is? just tool support of VHDL 2019? You now have everything as integers, which makes things easier.
There is nothing wrong with i_data or o_data... I am handling my port definitions very well as per my requirements in a broader sense... I am just asking you about how to make my constant c_mult a generic one. I got the point, you don't have an answer to my question. Or let's say my question doesn't make sense. Thank you for trying to help.To be honest though - I think I agree with barry - your code is a mess. Why cant i_data and o_data simply be unconstrained arrays of signed (either using the generics to size them, or ), rather than one huge std_logic_vector? It seems strange you're using VHDL 2019 for the internal code when the port definitions are straight out of 1993.
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