debugging low clock gating percentage during logic synthesis

[alokem]

Hi ,

What is the way of debugging low clock gating percentage (good amount of flops not gated by tool) during logic synthesis ?

Regards,
Aloke

 

[englishdogg]

simplest way would be to look at the report as a startpoint. Most common synthesis tools share the percentages of tool gated flops, non-tool gated flops and also the percentage of those whose enable is constant.

This should be simple enough. Another reason is the min threashold that you have set for a number of sink flops for a clock gating cell to drive. This impacts coverage as well.
But this needs to be well set cause this directly increases the number of CG elements in the design as well as area and impacts timing in some cases.

 

[alokem]

simplest way would be to look at the report as a startpoint. Most common synthesis tools share the percentages of tool gated flops, non-tool gated flops and also the percentage of those whose enable is constant.

This should be simple enough. Another reason is the min threashold that you have set for a number of sink flops for a clock gating cell to drive. This impacts coverage as well.
But this needs to be well set cause this directly increases the number of CG elements in the design as well as area and impacts timing in some cases.

Thanks for your reply . During synthesis run , I used 3 as the minimum number of flops to be gated per ICG and got approx 80%-85% clock gating
percentage . During debugging , I found that 15% - 20% flops can not be gated because tool is not able to find common enable for 3 flops as a cluster .
This I did by changing the minimum number of flops to be gated from 3 to 2 etc . This is OK as clock gating percentage number is 10% - 20%.

Now lets us consider a situation (though I have not yet faced but asking for learning purpose ) .. If the clock gatiung percentage number is say about 40% - 50% , then will there be difference in debugging compared to what I did earlier (mentioned above) ? Is there any other way except changing minimum flop count value to see the result ?

Thanks !

Aloke

 

[englishdogg]

It basically depends on the synthesis tools you are using and its reporting capabilities. But yes it is possible to the last minute level.

You can report ungated flops as well, there would be preview reporting as well from where you get an idea of your clock gating coverage and manipulate your Clock gating settings. Whatever output comes for anything you should be able to report and identify the reason.