cvc
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… Tuesday Technote on Solver Debug, Jijo PS, Srini TeamCVC www.cvcblr.com
Dealing with simple solver failure – looking for really “quick help”. It is a layered SystemVerilog code for a SAN Router. An inherited constraint in a testcase showed randomize() failure. Before you jump to conclusion on the simple nature of the problem – consider that this is the first time ever I look at this design/env as the original author moved out of the company (sign of good times ?) and am given to fix the code ASAP – in next 15 minutes that’s (sounds way too familiar, Huh?).
So what next? Consult our friendly Questa SolveDebug: add vsim –solvedebug and bang you go…
It does 2 things:
It prints the minimal set of conflicting constraints,
Creates a stand-alone test to reproduce the failure in a crisp testcase. See below:
Minimal set of constraints from user-code
Testcase being created by Questa (system verilog code, can be run standalone)
Now that was easy to fix, simply override the test-specific constraint in the inherited test_cfg than “adding to it”. Glad I met my deadline for today!
Hats off Questa – wish it prints the vsim –solvefaildebug automatically on such failures to log file.
TeamCVC
www.cvcblr.com/blog
Dealing with simple solver failure – looking for really “quick help”. It is a layered SystemVerilog code for a SAN Router. An inherited constraint in a testcase showed randomize() failure. Before you jump to conclusion on the simple nature of the problem – consider that this is the first time ever I look at this design/env as the original author moved out of the company (sign of good times ?) and am given to fix the code ASAP – in next 15 minutes that’s (sounds way too familiar, Huh?).
Code:
# Number of fware xactn 19
# ** Fatal: [Time 0 ns] Test cfg Solver failure
# Time: 0 ns Scope: san_rt_top.san_rt_test_pgm_0.b1.lp.a1 File: ../
rt_test_03.sv Line: 83
# ** Note: Data structure takes 9699728 bytes of memory
# Process time 0.03 seconds
# $finish : ../test/san_rt_test_03.sv(83)
# Time: 0 ns Iteration: 2 Instance: /san_rt_top/san_rt_test_pgm_0So what next? Consult our friendly Questa SolveDebug: add vsim –solvedebug and bang you go…
It does 2 things:
It prints the minimal set of conflicting constraints,
Creates a stand-alone test to reproduce the failure in a crisp testcase. See below:
Minimal set of constraints from user-code
Code:
# ../test/san_rt_test_03.sv(82): randomize() failed due to conflicts between the following constraints:
# ../test/san_rt_test_03.sv(59): san_rt_test_cfg_0.cst_reasonable_fw_xactns_1 { (san_rt_test_cfg_0.no_of_fware_xactions > 32′h00001360); }
# ../src/san_rt_fware_gen.sv(42): san_rt_test_cfg_0.cst_reasonable_fw_xactns { (san_rt_test_cfg_0.no_of_fware_xactions < 32′h00000032); }
# ** Fatal: [Time 0 ns] Test cfg Solver failure
# Time: 0 ns Scope: san_rt_top.san_rt_test_pgm_0.b1.lp.a1 File: ../test/san_rt_test_03.sv Line: 83
# ** Note: Data structure takes 9699728 bytes of memory
# Process time 0.02 seconds
# $finish : ../test/san_rt_test_03.sv(83Testcase being created by Questa (system verilog code, can be run standalone)
Code:
# ../test/san_rt_test_03.sv(82): randomize() failed; generating simplified testcase scenario…
# —– begin testcase —–
# module top;
#
# class TFoo;
# rand bit [15:0] \san_rt_test_cfg_0.no_of_fware_xactions ;
# constraint all_constraints {
# // ../src/san_rt_fware_gen.sv(42): san_rt_test_cfg_0.cst_reasonable_fw_xactns { (san_rt_test_cfg_0.no_of_fware_xactions < 32′h00000032); }
# (\san_rt_test_cfg_0.no_of_fware_xactions < 32′h00000032);
# // ../test/san_rt_test_03.sv(62): san_rt_test_cfg_0.small_tst_cst { (san_rt_test_cfg_0.no_of_fware_xactions < 32′h000013ec); }
# (\san_rt_test_cfg_0.no_of_fware_xactions < 32′h000013ec);
# // ../test/san_rt_test_03.sv(59): san_rt_test_cfg_0.cst_reasonable_fw_xactns_1 { (san_rt_test_cfg_0.no_of_fware_xactions > 32′h00001360); }
# (\san_rt_test_cfg_0.no_of_fware_xactions > 32′h00001360);
# }
# endclass
#
# TFoo f = new;
# int status;
#
# initial begin
# status = f.randomize();
# $display(status);
# end
#
# endmodule
# —– end testcase —–
#Now that was easy to fix, simply override the test-specific constraint in the inherited test_cfg than “adding to it”. Glad I met my deadline for today!
Hats off Questa – wish it prints the vsim –solvefaildebug automatically on such failures to log file.
TeamCVC
www.cvcblr.com/blog