dealing with output in a shifter

[Y.T_comp]

HI all ! I have new question :-D,

if I have a synchronised shifter module in VHDL have en,shr,shl,load,Din and Dout as ports :

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Code VHDL - [expand]
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entity shifter is
port(en:IN bit,Din : IN bit_vector(3 downto 0),load,shr,shl:IN bit;Dout : out bit_vector(3 downto 0)) ;
end shifter;
 
architecture arc of shifter 
signal shift_val : bit_vector(3 downto 0);
begin
process(shr,shl,load,en)
begin
if(en='1' and load='1') then 
shift_val<=Din;
elsif (en='1' and shr='1') then
shift_val(2 downto 0)<=Dout(3 downto 1);
shit_val(3)<=0;
else
shift_val(3 downto 1)<=Dout(2 downto 0);
shit_val(0)<=0;
endif;
end process;
precess
begin
if(clk='1' and clk'event )
Dout<=shift_val;
end arc;

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my question is why we didn't deal with output instead of using shift value .(just for delay problem?)
why i can't say for example :

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Code VHDL - [expand]
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Dout(3 downto 1)<=Dout(2 downto 0);
Dout(0)<=0;

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please explain this to me ! thanks .

best regards .

 

[std_match]

Your code has several typos and can't work, but I think I understand your question.
A port of type "out" can't be read inside a process, so it impossible to shift the current value.
The standard solution to this is to use an intermediate signal that can be read and also assigned to the output.

Another possibility is to use port type "buffer", but that will create problems if you don't do it strictly in all levels of the design. I don't recommend "buffer".

A third alternative is to use the attribute "driving_value". The current value that the process is trying to drive to a port of type "out" can be accessed with this attribute.

 

[Y.T_comp]

so it's true that the right signals on the assignment statement must br input or buffer or inout .

thank you std_match for explanation .