DDRII xilinx fpga IOBs flip flops

[Bustigo]

why the Flip Flops n IOBs of FPGA use 2 DDRII FlipFlop "double rate" although one operating at rising_edge and one on falling edge ....why not 1 for both or why double rate ??/

 

[joelby]

This is presumably because you want to convert the double rate data to single rate at the input pad. Hence, you need to be able to capture two bits per clock period. Thus you need two flip flops.

If you don't want to use DDR IOBs, you can use a SDR input and clock it at double the clock speed. This is perfectly acceptable as long as the FPGA can cope with the higher frequency.