Ddr2 simulation in hyperlynx

[jai_vardhan]

Hi all,
I am running DDRX wizard for 512mb ddr2 800 mhz ram. I have some confusion in the report generated after simulation about the column min rise time delay and max rise time delay and so on fall time min and max delay time. Plz anybody explore me what is actually report is talking about. I am attaching the report in pdf format where I have highlighted the column with yello.
Plz help me.

 

[mishrashashi]

Rise/Fall Delay errors indicates violation of minimum and maximum limits. You need to set delay limits in SI Net Spreadsheet.

The maximum pin delay is measured in the following way:
1. Find the time at which the input signal crosses the receiver threshold furthest away from the initial DC voltage. The furthest threshold provides the most pessimistic delay.
2. If the input signal crosses the further receiver threshold more than once, record the delay as the time of the last crossing.
3. Subtract the delay from the time required for the driver to switch to obtain the final delay value.

If you run batch simulation with all three IC model corners, all delays are calculated from the smallest driver switching times. This provides the most conservative results.

I think Hyperlynx user manual(see in help file, boardsim user manual) has this description. refer to batch simulation wizard for more details.

 

[jai_vardhan]

Thanks for Ur response Shashi and super like to ur quote also.