Thanks for all your replies,
I know the IP Core is apt for controlling the memory device, but it is too complex and hard to understand. I will be using the same for real world application but as far as my course project goes, I would just be required to build the controller with essential understanding of the translation of the client requests at one end to corresponding command sequences at the DDR end and effective testbench to prove its working. I wanted to know whether even if i am not able to achieve the maximum operational frequency, whether such an implementation of a DDR memory controller would make sense?