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DDR sdc commands

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promach

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Could anyone advise on

1. Why use UFF0 and UFF5 in the set_multicycle_path commands ?
2. Why use -divide_by 2 and -edge_shift {1.5 1.5 1.5} inside create_generated_clock commands ?
3. Why need two different create_generated_clock commands ?


Code:
# Credit :
# https://www.cnblogs.com/lelin/p/12652460.html
# https://zhuanlan.zhihu.com/p/339353879

################################ For READ operation #########################################

## operating frequency 200MHz

create_clock -period 5 -name DQS [get_ports DQS]

## positive-edge sampling delay

set_input_delay 0.4 -max -clock DQS [get_ports DQ]
set_input_delay -0.4 -min -clock DQS [get_ports DQ]

## negative-edge sampling delay

set_input_delay 0.35 -max -clock DQS -clock_fall [get_ports DQ]
set_input_delay -0.35 -min -clock DQS -clock_fall [get_ports DQ]

## launch and capture flops are of the same edge type

set_multicycle_path 0 -setup -to UFF0/D
set_multicycle_path 0 -setup -to UFF5/D


################################ For WRITE operation #########################################

create_clock -period 3 [get_ports CLK2X]
create_generated_clock -name pre_DQS \-source CLK2X \-divide_by 2 \[get_pins UFF1/Q]
create_generated_clock -name DQS \-source UFF1/Q \-edge {1 2 3} \-edge_shift {1.5 1.5 1.5} \[get_ports DQS]

set_output_delay -clock DQS -max 0.25 -rise [get_ports DQ]
set_output_delay -clock DQS -max 0.4 -fall [get_ports DQ]
set_output_delay -clock DQS -min -0.15 -rise [get_ports DQ]
set_output_delay -clock DQS -min -0.12 -fall [get_ports DQ]
 

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