[SOLVED] DDR 2 Clarifications--Need your help

[techzee]

Hi,

I am working with Hyperlynx tool and currently going to simulate DDR667Mbps. I have clarifications to make :
1. what is the frequency of operation for Data, Address, DQS and Clock signals for which i need to simulate for this case DDR 667mbps?
2. Is it true that the address lines will be operated at half the frequency of data lines?
3. What is the purpose of DM Signals?
It would be great if I could find some help.


Thanks

 

[qieda]

Hi,

1.
Data (DQ,DM) = 667 MHz
Address (A, BA), Command (RAS,CAS,WE,CS,CKE) = 333 MHz
Clocks (CK, xDQS) = 667 MHz
2.
addresses can change with every clock cycle, but this means we have half the clock frequency
example
address go high with clock edge 0 and low with clock edge 1
due to this maximum frequency is half the clock frequency
3. DM = Data mask signal
it validates the DQ during a write access

 

[qieda]

Hi,

sorry I wanted to attach this file
https://download.micron.com/pdf/datasheets/dram/ddr2/1GbDDR2.pdf

 

[techzee]

Thanks qieda. When simulatinf for many interfaces I could see lot of non-monotonic regions. What could be the reason for it and how can we eliminate it? any help will be great and useful

 

[qieda]

Hi,

I'm not familiar with Hyperlynx.
So for my understanding
you simulation shows the impedance of your PCB traces and you see non-monotonic there.
Is this the correct understanding?

I think reasons could be vias, or non-monotonic neighbourhood.

regards

 

[techzee]

Yes it cud be because of impedance mismatch but the frequency of operation is very low say in MHz, How far will the effect of reflections is present on the line.
Which software you use?

---------- Post added at 17:56 ---------- Previous post was at 17:55 ----------

The speed i meant was 40Mhz.

 

[qieda]

Hi,

I'm sorry I never used software. (only HW ;-) )

as far as I know reflections depends on the rise/fall time. So the operation frequency do not matter.
Calculations for PWB Trace Termination and Reflection values

Other points you can think of
How to handle the termination, which is defined in DDR2?
How many DRAMs are connected to your interface?
(e.g. if you have connected two parts, do you do a star configuration or a fly-by configuration)

regards

 

[allanvv]

The speed i meant was 40Mhz.

What is 40MHz? Earlier you stated that you wanted to use DDR2 at 667Mbps.

 

[techzee]

allnav,
Yes I wanted to use DDR, I was simulating local bus in my board at 40Mhz, I got some non-monotonic.
I got an idea of eliminating it,
because of many branch points in the topology, the chips are getting loaded. Henceforth I did some adjustments wit the length near the branch and i could see some good results at the end.