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DDR(2/3) Memory Performance

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Jun 26, 2011
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I am developing a design for a new microarchitecture as part of a research project. I am using VHDL to create a model of this architecture . Our goal is to estimate the performance of this architecture from simulation results, and not necessarily to actually get it running in a chip. Eventually, we will protype it on an FPGA if our simulation results are positive.

We envision the architecture to include a memory controller for DDR2/3 memory. One phase of the algorithm involves streaming through a large number of data items in the DDR memory (up to 2 million 256bit data elements) and counting how many of a certain type there are in this list. Multiple passes are potentially required.

We simply want to estimate how long it would take (in clock cycles) to read in a certain number of data elements from the DDR. That is all the information we require.

My question relates to the assumptions we are currently making. We are assuming that if, for example, the data width of the DDR is 256-bit, then we can read in a 256-bit data item once in every cycle. Therefore, to read 1 million 256-bit words, it will take one million cycles.

Is this a realistic estimate of the number of cycles it would take in a real circuit? Or are there factors (for example, refresh cycles) that would render the values we are deriving from the assumption above to be very inaccurate? As long as we are within about 5% of the actual value, that would be acceptable.

Thanks very much for any replies.


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