dc_compiler: setting input_delay and output_delay for feed through paths

[TonyLS]

I have many paths that start at an Input pin, goes through combo logic, then to an Output pin. What complicates things is that the Input can fanout to a flop as well as an Output. Also the Output can be driven by multiple sources (flop, Input) via a mux structure.

The flow sets generic Input and Output delays (65% and 45%). The problem with the feed-through paths is that it's impossible to make timing because the entire path is consumed by the 65/45 delays. However removing or reducing the delays isn't an option either because the Input can fan out to a register as well as the Output. Removing or reducing the Output delay isn't an option because it may be sourced lets say from a flop through a mux to the Output as well as the Input path.

I tried setting a set_max_delay -from Input -to Output but the original set_input_delay and set_output_delay are still in effect resulting in more delay being added to the path

Any ideas?

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I think I got it. I can assign a virtual clock and assign input_delay and output_delay constraints based on the virtual clocks. The feedthrough paths are essentially ASYNC so no other clock source will be in the feedthrough path. The original input and output delay constraints that reference the functional clock will still be in effect. Will dc_compiler swtich between the two types of paths and bring in the right delays?. Switch between the virtual clock and a reduced input and output delay for feedthrough paths and a flop based path using the functional clock and tighter IO delays??

 

[slutarius]

I dont think you need the original boundary constraints if you have already applied them with virtual clocks.

 

[bikerboy21]

DC should analyze timing on the worst case events on those start/end points, whether it's a pin or port. Overloading the port constrains with virtual clocks may introduce timing events that may not represent the actual operation of the design.
I recommend researching set_clock_groups to accurately constrain your design and avoid unnecessary runtime costs.