DC Synthesis error while simulating System verilog module

[satyakumar]

Hi all,
Im desiged an asynchronous FIFO in system verilog, and the module ports defined are using package declaration

eg: module afifo( input package_def::struct_def struct_inist,
input logic port1,
output logic port2);

And I tried to synthesize using DC, but it gave synthesize error on package declaration saying unsuported construct.

I didn't get any problem while doing simulation, my doubt is does DC won't support this type of port declaration.

Thanks to all

 

[sumit_techkgp]

It means dc dosent support that construct. U can consult synopsys regarding that
Sumit