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dc non-convergence in reference circuit

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Mar 30, 2007
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as the picture shows, the first reference circuit generates a global 1.5v voltage for the whole chip, then in ir receiver module, there is another reference circuit using 1.5v to generate the voltage of ir module (1.45v, 1.2v, 0.75v, 05v, 0.1v), and at every node, there is a 1pF mos cap. when simulating the first reference with bandgap seperately, it works well; when simulating the ir module with the second reference circuit (with ideal voltage source vdc=1.5v at second reference input), the ir module works well too; but when i simulate the whole circuit as the picture shows (first 1.5v reference + second reference + ir module), the dc operating point is of non-convergence, and the 1.5v voltage becomes to 2.1v (vdd=3v) for 3v/ss/-40deg corner, becomes to 1.04v for 2.7v/ss/-40deg, and other undesired value for other corner. very strange, i wonder why. what is the possible reason?

* Do you have 2 volt sources connected directly together? The simulator may not allow it.

* Do you have 2 ground references, either of which is legitimate by itself, but together they produce paradoxical volt levels at nodes? (Try changing ground icons to a voltage source of definite value.)

* Do you have a mosfet gate being driven at a paradoxical volt level outside of its supply rails? This can easily happen with a P-device particularly, if we forget to set the driver (op amp) to produce a usable output range.

* A simulators may not like it when 2 capacitors are in neighboring wires and those wires contain only a capacitor and nothing else.

for BradtheRad question,
* i don't have 2 volt sources connected directly together;
* i don't have 2 ground references;
* i don't have a mosfet gate being driven at a paradoxical volt level outside of its supply rails;
* i don't 2 capacitors are in neighboring wires.

but i still is of non-convergence, wrong voltage output for 1.5v reference.

You may try by initializing the 10pF capacitor with a value close to 1.5V. Also, are the opamps transistor level or macro model?

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