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Biasing Circuit in Cutoff region

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aishakhan

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I'm designing this biasing circuit in Cadence Virtuoso, but all the transistors are coming in cutoff region. I've targeted the paper "Design of Voltage–Current Reference Source in CMOSTechnology". I don't understand the reason why, I've kept the width and length as mentioned in the paper, but I don't understand why all transistors are in cutoff, could anyone explain why?
 

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