When doing DC-analysis in cadence (IC5033) and printing the dc operating points, I find that some of the given capacitance values are negative. What does this mean?
and where can I find the description of the too many capacitances given by the dc-analysis?
Which model do you use ?? DC analysis may give some capacitance values depending on bias but these should not be negative..
If so, the is a problem of modelling.
In additional to, first versions of 5.033 may have some bugs that computes some parameters of a active device. Because evolution period of 5.033 isn't finished.
If a capacitance value is negative, it means that is an inductance !! It's so weird...??
In additional to, some design kits need some corrective verilog scripts ( for instance, for Bf there may be Gauss equation that creates a possibility variations etc..) Cadence interprets first them and then computes the equations.
I think the your design kit has some bugs...
One last point :Some parameters which start with C could not be a capacitor, they might be an internal variables...
BSIM3v3 models show negative cap values over the operating range. The default setup of CDS only show CGS, CDS, CDG ... . The negative caps are only seen in result text file which show more details.
i think getting the negative capacitance is because of the direction of the current and the variation of q.that causes the negative sign in derivetive equation.