data transfer from slower to faster clock doamin

[HPC]

Hi,

In my design I have two clocks CLKA (200MHz) and CLKB (450 MHz).
I need to transfer 16 bit data from CLKA domain to CLKB domain.

My data changes every clock in CLKA domain.

How do I sample this data in clock B domain correctly?

Thanks in advance.

 

[babaduredi]

Hi HPC,
There are 2 methods you can do that:
1.Using traditional handshaking mechanism or
2.Using asynchronous FIFO memory

method 1 is not preferred when clock latency is the concern.
So if you have enough hardware resources, i recommend you to go for method 2.

Design of asyn FIFO is bit difficult if you are beginner but it's widely used for data transmission b/w diff clk domains.
You can refer attached documents for the design of such FIFO:

I would recommend to design sync FIFO(FIFO1.pdf) first and than move to asyn FIFO(FIFO2.pdf).

 

[naught]

the two PDF are very helpful, thank you babaduredi!

to HPC, if you want save the trouble understanding the mechanism, just use the IPcore that is already embedded in the Xilinx EDAtool.

 

[HPC]

Thanks babaduredi and naught for information. Attachments really useful.
What I was thinking is to generate a control signal in clock domain A and toggle it when data changes in domain A.
Then edge detect this signal in domain B (detect both possitive and negative edges) and sample data accordingly.

 

[tariq786]

Thanks babaduredi and naught for information. Attachments really useful.
What I was thinking is to generate a control signal in clock domain A and toggle it when data changes in domain A.
Then edge detect this signal in domain B (detect both possitive and negative edges) and sample data accordingly.

Dude be careful. My first thought is that this might not work. You have CDC (clock domain crossing) problem. Use the proper protocol to transfer data from one clock domain to the other.

Look at this article

**broken link removed**

 

[mutant_corpse]

While transferring data from a slower domain to faster domain, we can clock gate the faster clock every alternate cycle. This is same as a multicycle path of 2. But it is all governed by the architectural requirements. A sneak peek into multicycle paths can be found here: https://vlsi-soc.blogspot.in/2013/03/multi-cycle-paths-perspective-intent.html