Data path between different clock domains

[nemolee]

Does anyone know, how can I do if the data bus across from one clock domain to another clock domain? I know one mehtod, but it is not a good one. The method I know is that adjusts the clock tree to let two clock domain meet your requirement.
But you have to spend too much time to do this. Does anyone know best way? Thanks.

 

[masai_mara]

I dont know how effective is your method but dosent seem to be much reliable. This problem is called clock domain crossing and widely encountered. to tackle this asynchronous behavior the data coming from the first clock domain is registered twice in the second clock domain before further procesing.
You can find relevant material discussing this at cliff cummings site.
http://www.sunburst-design.com/papers/

 

[xworld2008]

You can to www.edn.com , just few month ago it have a post about this.

 

[sarath51]

Even SNUG and Solvent has some papers

 

[nemolee]

Sorry. Can you explain more detail? There are too many papers in that wab. How should I know which paper is presented clock crossing? As I know, if the first register have time violation, setup/hold time violation, to cause the latched data error. The second register has error data too. They can't solve this question.

 

[xiongdh]

Sorry. Can you explain more detail? There are too many papers in that wab. How should I know which paper is presented clock crossing? As I know, if the first register have time violation, setup/hold time violation, to cause the latched data error. The second register has error data too. They can't solve this question.

the paper's title: Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs
registered twice in the second clock domain can decrease the probability of violation,it can be taken as one effective way to ensure reliability.
but for databus,More than two signal need to cross clock domain.You can not use this way,the reason is explained in the above paper.
Maybe you need to use handshake.
The 2004,07 EDN chinese version,this multiple clock domain was covered.the author is Mike Stein,Paradigm Works.I know the article's chinese title not English title.You may find it by author.

 

[nemolee]

Thank you for your useful help. I use the FIFO architecture show in above paper. I already solve my problem data bus between clock domains. But I use registers, not dual port memory, as my FIFO. There is no any timing violation again. I feel very good. Thank you to everyone.