Data Multiplexing using triStates?

[Joyee]

As we know, data multiplexing is often applied and two main implementation methods are prevalent in FPGA of Xilinx, say Spartan. They are BUFT and the combination of MUX and LUT.

However, in practice, some expericense informs us that BUFT is not recommended due to its simulation mismatch and poorer performance. Also just for this, Synplify automatically translates a MUX into gates regardless of whether the use of 3-states has been specified.
Altera also declare they don't support internal tri-state but just emulate it by MUX.

Therefore, what I wonder is anybody has the successful case for the utilization of internal tristate. If somebody does have, could he or she remind me where should be paid more attention to during the utilization. (As for the second questions, I wonder the details except that such as one cycle that shutdown all tri-state gates should be inserted between one transaction and the other).

Thanks in advance!

Joyee

 

[armer]

tri state buffer

I want to know that why you have to use tri state to implement mux?

 

[Joyee]

I just try to implement my design by tri-state. If all mux can be implemented by LUTs and LUTs can play better performance than tri-state, why does Xilinx provide internal tri-state gates?

 

[armer]

tri state

Use tri state, the bus can drive more fanout and is easy to implement . but as we write code, we rather use mux to implement the disign.

 

[Joyee]

ok, I see. Thank you Armer

 

[apsim]

HI，

I NEED 8 WAY Analog Multiplexers
WHO have it and DOC?

THANKS
APSIM

 

[njbibin]

for analog mux see 4051 and 4052

for buffers 74244

 

[andy1]

Tristate may consume more power since they cannot be turn on and off at the same time. When more than one is on at the same time even if momentarily, there might be a path from power to ground which cause a lot of currrent to ground.

Actually, Intel library uses analog pass gate and a decoder to impliment mux. At the output, they have a couple of feedback buffers to keep charge from leaking and prevent noise also. This configuration is used in custome circuit design and keep the gate count and area to a minimum.