As this is a Zynq any peripheral that is not included as part of the PS is going to be in the PL, which being configurable with an HDL means that the latency of the entire path isn't set in stone.
Arbitration overhead will have to account for the number of things being serviced, which can vary and the arbiter itself add varying amounts of latency depending on the implementation. To determine the latency to a memory on the AXI would require analysis of a worst and best case scenario of the access knowing the arbitration latency and the PS latency for the access.