Re: Data into a FPGA
Hi engr.ja,
please excuse me for the no complete question.
I mean the following:
I´m searching a short and easy way to save a lot of datastreams into the APA FPGA from ACTEL. It´s possible, to save the data into the sram, but this isn´t what I will do.
In other programming languages (for example: C) you can define variables with values, but if you do this in VHDL and you compile (synthesis) your design, the data (variables with values) won´t keep into the FPGA.
Normaly the FPGA make a netlist from the design (VHDL code) and isn´t able to save the values from the vhdl code.
I would like create somethink like this:
data := "10101011"; -- data
data2 := "00101011"; -- more data
...
...
output1 <= shiften(data); -- no correct code for shiften
output2 <= shiften(data2); -- no correct code for shiften
The datastreams should go on a output with a shiftregister
Is there a trick to do this?
Speedy750