DAC (digital to analog converter)

[faiq khalid lodhi]

can any one provide me the basic circuits of the DAC in Cadence without using the resistance.

 

[leo_o2]

You can use capacitor with charge sharing for DAC.

 

[faiq khalid lodhi]

but in very small technology i.e. 65nm the it is very difficult to make the DAC by using the charge sharing. So can any one suggest some solution of this problem.

 

[siilviu]

What is the resolution of your DAC?
For IC DACs, a "current steering" topology might be helpful because you dont have cappacitors neither resistors to integrate (which consume large area) but the chip becomes larger for 12 or more bits and also the decoding circuitry becomes more complex.
The basic idea is to steer a current into a current source by biassing or not a pair of two NMOS transistors (complementary biassed).
I can provide you some basic circuitry if you are interested in this topology.

 

[3imad]

Current Steering bassed Current mirror is good because hase servel performace

 

[faiq khalid lodhi]

i am really interested in this topology
i shall be very thankful to you if you will provide some basics

What is the resolution of your DAC?
For IC DACs, a "current steering" topology might be helpful because you dont have cappacitors neither resistors to integrate (which consume large area) but the chip becomes larger for 12 or more bits and also the decoding circuitry becomes more complex.
The basic idea is to steer a current into a current source by biassing or not a pair of two NMOS transistors (complementary biassed).
I can provide you some basic circuitry if you are interested in this topology.

 

[ammu1]

can anyone help me how to choose the transistor sizes for binaryweighted currentsteering dac with 65nm design.

Iam atttaching my design**broken link removed**.
Presently iam using the values

srcwidth=cscwidth=swichwidth=10um
srclength=csclength=switchlength=1um

but iam getting the outputimpedence at 100MHz -15dB it is too low value.If i decrease the transistor sizes then region of transistors are in linear region.

anybody suggest the transistor sizes for improving the outputimpedence and also the transistors are in saturation region.

---------- Post added at 13:41 ---------- Previous post was at 13:22 ----------

The schematic design is