You should post the schematic you are discussing - but I think you are working with the DFF made of multiple diff pairs.
In this device, either the input amp or the latch is biased since they are fed by one diff pair. When the amp is on, the latch is Hi-Z because it has no bias fed to it.
The amp buffers the D signal during the CLKB time, and upon the rising edge of the CLK signal, the D-amp is unbiased and the latch is biased.
Although it can be said that the BC capacitance is holding the voltage, really, the case is that during crossover from CLKB to CLK, the bias is steered from the input amp to the latch amp so as the input amp begins to lose bias, the latch amp begins to increase bias. At the midpoint, both amps are sharing the bias and reinforcing the state rather than both amps being off, and capacitance alone holding the state.
I would call it more of a handoff between amps then a case of capacitive holding like DRAM.