D-latch setup time calculation with data transition time

[yogi.uniyara@gmail.com]

hello ,
can anyone please help me , that my set up time is independent of capacitive load and i am not getting any explanation for that. i extracted my h spice net list from cadence virtuoso layout editor with 45nm technology.also, my setup time is linear with data transition time up to 150 p transition time(data) .is it possible? any explanation for linearity is required.
please help me in that.THANKS in advance.

 

[haykp]

Hi Yogi,

First of all flop setup time doesnt depend on output load. It depends only on flop internal characteristics.
I recommend you to read the following article to understand the setup/hold characteristics of flop: Timing Characterization of Dual-Edge Triggered Flip-Flops.

If you can share some waves I can dive deeper on this.