I read in a book that the Clear and the Prest of a D Flip Flop are asynchronous inputs...
I doubt...The clear shall not propagate to the RS FF section unless the D is 0 and CLK high....and the PRESET shall not have effect unless CLK=1 and D=1....
So How really to use a D FlipFlop with Prest and Clear ?
And am I right to say that a the PRESET and Clear are a way to bypass the CLK and use the D Flip Flop as an RS Flip Flop ?
The CLEAR/PRESET are asynchonous, ie they are independent of clock edges. In otherwards, they apply instantaneously and have precedence over clock transitions. Clocked operation will only occur when both are high. **broken link removed** pretty much summarises it.
preset and clear are asynchronous inputs .whenever preset is 'active' irrespective of input and clock the output of flipflop becomes high.and in case of active clear input the output of flipflop becomes low irrespective of input and clock
If D and CLK are high, S=1 and R=0 (RS FF Section...) and now if I want to clear the FF the preset will not propagate to the flip flop...as they are and Gated...R=0 shall propagate only if CLk =1 and D=0
I do not know which particular FF you are referring to, but if the datasheet says that the set andd reset inputs are asynchronous, that means they operate independently from the clock and data inputs. Once asserted, they will force the output in one of the possible states, even if there is a clock signal present and regardless of what the data input is. The effect is immediate.
Perhaps it would help if you posted the schematic you are referring to.
Preset and Clear are asynchronous. The drawing from the book it's only for explanation purpose and it' s possible that the author didn't spot that's wrong. Here is the Texas Instruments implementation for D flip-flop
For synchronous case, the changes in output is depend on the clock. Even you give reset (preset) to low, output Q can't go to 0 (1) immediately, and have to wait until clock pos edge.
For asynchronous case, whenever clear(preset) is low, the output Q will be 0(1) immediately. No need to wait the clk pos edge.
(I just mention for the case of 74ls74 D flipflop, active low clear and preset, and pos edge clk)