D Flip flop clock design

[haykp]

Dear Forum,

The attached picture is a schematic diagram of a Dff.

As can be seen in that diagram the first input TG clock is CL and not CLK.

What is the reason of this? Why we cannot conect the CLK to the clock of first TG.

Thanks,
Hayk Petrosyan

 

[pancho_hideboo]

What is the reason of this?

Simply for buffering.

 

[haykp]

Could you please expand more. I have a feeling that this is done for setup/hold timing.

 

[pancho_hideboo]

I have a feeling that this is done for setup/hold timing.

No.

Do you understand an operation of this master/slave D-FF ?

 

[haykp]

Yes,
And I clearly see your point.

Thanks,