haykp
Member level 3
Dear Forum,
The attached picture is a schematic diagram of a Dff.
As can be seen in that diagram the first input TG clock is CL and not CLK.
What is the reason of this? Why we cannot conect the CLK to the clock of first TG.
Thanks,
Hayk Petrosyan
The attached picture is a schematic diagram of a Dff.
As can be seen in that diagram the first input TG clock is CL and not CLK.
What is the reason of this? Why we cannot conect the CLK to the clock of first TG.
Thanks,
Hayk Petrosyan