NiGHTS
Newbie level 1
Hi, I am new to this forum. I hope I am posting this question in the right place.
I am developing on the Cypress CY7C63823. I am working exclusively in the Assembly language. I am using the Cypress PSOC Designer 5.1 IDE and compiler. I am developing a simple SPI 3-wire system that communicates between two identical cypress microcontrollers. One is configured to master and the other is configured to slave.
The problem I am having is with the slave. Normally the master firmware is constantly requesting data from the slave. The slave does in fact respond as expected, but apparently this is causing the slave's main loop to stop looping, yet my SPI handler still responds to interrupts. This leads me to think that there is a problem with the way I am dealing with the interrupt in the first place -- a stack issue of some sort.
The interrupt starts at the boot.asm like this:
This handler causes the main loop to stop working:
Meanwhile, this is what my main code looks like:
Interestingly enough, removing the 2 line's of SPI_Handler code occuring at ".SPI_Handler_Loader_Wait:" fixes the problem, but without this code there is no way to tell if the SPI data has completed receiving the entire byte from the master.
I have looked in PDF's and google for "best practice" in this situation. I can't find any information anywhere on how to handle this. Any help is appreciated!
I am developing on the Cypress CY7C63823. I am working exclusively in the Assembly language. I am using the Cypress PSOC Designer 5.1 IDE and compiler. I am developing a simple SPI 3-wire system that communicates between two identical cypress microcontrollers. One is configured to master and the other is configured to slave.
The problem I am having is with the slave. Normally the master firmware is constantly requesting data from the slave. The slave does in fact respond as expected, but apparently this is causing the slave's main loop to stop looping, yet my SPI handler still responds to interrupts. This leads me to think that there is a problem with the way I am dealing with the interrupt in the first place -- a stack issue of some sort.
The interrupt starts at the boot.asm like this:
Code:
org 10h ; SPI RX Full Interrupt Vector
ljmp SPI_Handler
retiThis handler causes the main loop to stop working:
Code:
SPI_Handler:
M8C_DisableGInt
push X
push A
.SPI_Handler_Loader_Wait:
TST REG[INT_CLR0],INT_MSK0_SPI_RX ; Address transfer complete?
JZ .SPI_Handler_Loader_Wait
; Code goes here, but even without code the problem occurs
pop A
pop X
M8C_EnableGInt
retiMeanwhile, this is what my main code looks like:
Code:
AREA text(ROM,REL,CON)
_main:
; Enable SPI
lcall SPIM_1_EnableInt
; Configure SPI: Clear Swap
AND REG[SPICR], ~(SPIM_1_SWAP)
; Configure SPI: Set slave mode
and REG[SPICR], %11101111
OR REG[SPICR], %00100000
; Enable Interrupts
M8C_EnableGInt
Main_Loop:
; As soon as the first interrupt is fired, this loop is no longer in service
jmp Main_LoopInterestingly enough, removing the 2 line's of SPI_Handler code occuring at ".SPI_Handler_Loader_Wait:" fixes the problem, but without this code there is no way to tell if the SPI data has completed receiving the entire byte from the master.
I have looked in PDF's and google for "best practice" in this situation. I can't find any information anywhere on how to handle this. Any help is appreciated!
