Cycle simulators:
Preprocess the design into a symbolic representation
— Levelized Compiled Code (LCC)
— Binary Decision Diagrams (BDD)
— Boolean and arithmetic operations
Update all circuit states simultaneously when triggered
— Using lookup tables and computational methods
— Typically on an externally defined clock edge
— The software counterpart of a hardware model
Event simulation typically traces every signal transition as it propagates through the
circuit, and continues to do so until the circuit reaches a stable state. The illustration
displays part of an event trace produced by the Verilog-XL simulator. Note that the
simulator may need to calculate the state ofa component several times during the same
simulation time instant.
Cycle simulation typically re-evaluates the state of the circuit as a whole, once upon
each external trigger, usually without evaluating any intermediate node states. Cycle
simulation can implement combinational control logic as an optimized lookup table.
Cycle simulation can map vector functions, data flow, and arithmetic calculations into
native machine instructions. For example, it may implement a multiply operation in
machine instructions, rather than as a lookup table.