shreyakishore
Newbie level 2
I am trying to test a VHDL code for 4x4 array multiplier and passing it through a Verilog testbench.
I am attaching all the code files I have used. I used a separate file to define all the component entities and then a main file for the multiplier.
The testbench is in Verilog code. I don't have much clue about Verilog and the testbench was provided to me.
On running the command ncverilog with the file names, I am getting this error.
I am at my wit's end trying to figure out the problem. I would be very grateful if someone can help me out with this.
I am attaching all the code files I have used. I used a separate file to define all the component entities and then a main file for the multiplier.
The testbench is in Verilog code. I don't have much clue about Verilog and the testbench was provided to me.
On running the command ncverilog with the file names, I am getting this error.
I am at my wit's end trying to figure out the problem. I would be very grateful if someone can help me out with this.