Customized Capacitor Design

[niloufar-navidi]

Hi,

I'm trying to design a customized capacitor in Cadence, IC16. I use TSMC 65nm PDK, and the extraction tool is Calibre. What are the layers that make the extraction tool understand that my device is a capacitor?

Thanks

 

[Dominik Przyborowski]

All you need is pins on schematic and metal layers on layout.

Can you elaborate your issue a bit more?

 

[niloufar-navidi]

A few more notes about this question:
1- I'm trying to draw a simple MOM capacitor
2- Top plate consists of M5 and M7 which are connected through vias
3- Bottom plate is made up of M6
This is my question:
When I draw the capacitor that I explained above, and after running LVS, I get "Nothing in Layout", and "Nothing in Source" errors, and LVS doesn't complete.

1-Please let me know what I can do to pass this LVS?
2-What are the layers that make the extraction tool understand that my device is a capacitor? Where can I find the relevant layers?

Thanks for your help

--- Updated Aug 26, 2020 ---

All you need is pins on schematic and metal layers on layout.

Can you elaborate your issue a bit more?

Thanks for your reply.
I have just added a few more notes to my question.

 

[Dominik Przyborowski]

You have to add pins both to schematic and layout. That's all. Have you add them?

 

[niloufar-navidi]

You have to add pins both to schematic and layout. That's all. Have you add them?

Yes, I have done that.
Here is the schematic:

Here is my layout consisting of M1, M2, OD, dummy layers, and the ports:

 

[Dominik Przyborowski]

If terminals on layout are placed with proper layers/purposes (I don't see labels for pin on layout), what might help is addition of lvs metal resistor(s).
They should be in tech lib lvsres or sthing similar. Place them between at least one terminal and one plate.

BTW is connectivity clear in XL?

 

[niloufar-navidi]

If terminals on layout are placed with proper layers/purposes (I don't see labels for pin on layout), what might help is addition of lvs metal resistor(s).
They should be in tech lib lvsres or sthing similar. Place them between at least one terminal and one plate.

BTW is connectivity clear in XL?

I have attached an image of the pin properties.

I looked in TSMC 65nm library but couldn't find anything that looked like a dummy resistor (LVS RES as you said)!
The connectivity is also clear.

 

[slizak]

The screencapture of RVE shows a big red warning that it could not determine the power and ground, which means as far as LVS is concerned, there is no current flow, so there are no parasitic effects.

What does the design manual in the PDK say in regards to setting up power and ground? The Calibre examples all use VSS and VDD as power and ground net names. Might need to identify whatever you are using in the Calibre Interactive LVS screen.

 

[Dominik Przyborowski]

Exactly, did you added gnd! Label on sx (maybe sxcut not sure) on the Substrate?

 

[dick_freebird]

Extraction may need "bulk" or some similar layer.

Schematic could maybe use a pcapacitor between
the pins, of roughly-right value if you want circuit
simulation to be realistic.

 

[timof]

LVS "understands" where the device is using "device recognition" concept.
Device recognition includes layers for the "seed" and for the "terminals", that are derived by LVS from the original layout shapes.

You can look it up how the devices are formed in design rule manual.

Also, you can open Calibre LVS rule deck, and see how the devices are formed.
Search for lines starting from "DEVICE" statement.

Some devices may need some kind of marker layers, to be recognized properly.
Some other devices do not need marker layers, their recognition layers are derived from layers like poly, diff, nplus, pplus, etc.

Very often, MOM and MIM capacitors are generated from PCELLs, with some fixed geometries, that are characterized by the fab, and described by SPICE models.

You can include MOM capacitors into your SPICE simulation in two different ways:

1. treat them as devices, in which case LVS should recognize them as devices.

2. treat them as interconnect parasitic capacitance, in which case they should not be recognized as devices.

It's easy to make a mistake, and make MOM capacitance counted twice (by SPICE model and by parasitics).